Latches are the fundamental bi-stable memory circuit in digital systems to store data and indicate the state of the system. In this project, we are going to implement and simulate the basic NAND cell of an SR-Latch and see how it functions.
|1||Digilent® Nexys™4, Nexys™3, Nexys™2, or Basys™2 FPGA Board|
|1||Xilinx ISE Design Suite: WebPACK (14.6 Recommended)|
Figure 1 below shows an implementation for SR-Latch with NAND implementation. According to the truth table on the right, S and R are active low. When only S is asserted (S is '0'), the output Q is SET to '1'. When only R is asserted (R is '0'), the output Q is RESET to '0'. When neither S and R are asserted, the output holds its previous value.
SR-Latch is a kind of bi-stable circuit. However, due to propagation delay of NAND gate, it is possible to drive the circuit into metastable state, where the output is oscillating between 0 and 1. The metastable state will be triggered when neither the set operation nor the reset operation propagates through the whole cell before the cell changes to the hold state.
Assume the NAND gates in SR-Latch have a delay of 1 ns. The Verilog file for the SR-Latch looks like follows:
`timescale 1ns / 1ps module sr_latch( input S, input R, output Q, output Qn ); wire Q_int, Qn_int; assign #1 Q_int = ~(S & Qn_int); assign #1 Qn_int = ~(R & Q_int); assign Q = Q_int; assign Qn = Qn_int; endmodule
For the purpose of demonstrating the functionality of SR-Latch, we consider the following input simulus:
The codes in the test bench looks as follows:
initial begin // Initialize Inputs S = 1; R = 1; // Add stimulus here #100 S = 0; #100 S = 1; #100 R = 0; #100 R = 1; #100 S = 0; R = 0; #100 S = 1; R = 1; #100 S = 0; R = 0; #100 ; end
Figure 2 below shows the simulated waveform of the circuit; at 300 ns, Reset signal is asserted. From the zoomed-in graph on the left, it takes 2 ns for Reset operation to propagate through the NAND cell. At 600 ns, both S and R toggles from 0 to 1, resulting in a change between an unfinished SET/RESET operation directly to hold state, which finally triggers an astable state (usually referred as meta-stability).
Now that you've completed this project, try these modifications:
|Time||SET||RESET||NAND Cell||NOR Cell|
HINT: An SR-Latch is driven into metastability by issuing a store operation before a set or reset operation is finished. Similarly, the D-Latch can be driven into stability by issuing a latching operation before the new data is updated to the D-Latch.