In this design, you are going to use a chain of flip-flops to implement a shifter register. The shifter register will be clocked using the clock divider you built in previous projects.
|1||Digilent® Nexys™4, Nexys™3, Nexys™2, or Basys™2 FPGA Board|
|1||Xilinx ISE Design Suite: WebPACK (14.6 Recommended)|
When the reset button is pressed, LED0 is on while LED1 to LED7 are off. When the reset button is released, the light keeps shifting from LED0 all the way to LED7 and back to LED0 at a frequency of 0.74Hz.
There are different ways to design the system. Two block diagrams of the system that fulfills the requirements are shown in Figs. 1 and 2 below. You are always welcome to come up with your own design.
Here are some sample codes that you can refer to:
always @ (posedge(clk), posedge(rst)) begin if (rst == 1) Q <= 1'b0; // Q is reset to 0 else Q <= D; end
always @ (posedge(clk), posedge(rst)) begin if (rst == 1) Q <= 1'b0; // Q is reset to 0 else Q <= (A & B); end
Now that you've completed this challenge, try these modifications: