Stop Watch

Design Challenge 7

Design Challenge:

Stop Watch


In this design challenge, you are going to be asked to put combinational circuits, sequential circuits, and state machines together and design a stopwatch on the FPGA board.

Before you begin, you should:
  • Have the Xilinx® ISE WebPACK™ installed.
  • Have your FPGA board set up.
  • Be able to code combinational and sequential circuits behaviorally and structurally in Verilog HDL.
  • Be able to design and implement state machines to encode the functional description of a digital system.
After you're done, you should:
  • Be able to design a complex digital circuit using state machine, combinational circuit, and sequential circuit components.


Qty Description
1 Digilent® Nexys™4, Nexys™3, Nexys™2, or Basys™2 FPGA Board
1 Xilinx ISE Design Suite: WebPACK (14.6 Recommended)
1 Digilent Adept


In this design challenge, you need to create a four-digit stopwatch on your board, using the seven-segment display as an output device. The stopwatch should count from 0.000 to 9.999 seconds and then roll over, with the count value updating exactly once per millisecond. Each time the counter rolls over, update a 4-bit binary counter and display the bits on four digits of the seven-segment display.

The stopwatch requires four push-button inputs: start, stop, increment, and clear (or reset). The increment function should cause the displayed count value to increment once each time the button is pressed, regardless of how long the increment button is held down.


Here, we provide you with a partial/incomplete block diagram as displayed in Fig. 1 below.

Figure 1. Stopwatch block diagram.

According to the block diagram in Fig. 1, you have built some of the blocks already in the previous projects or design challenges, e.g., seven-segment decoder, 4-1 bus mux, clock divider, 2-4 decoder, and 2-bit binary counter. The new blocks you need to design at this time are the controller block and the decimal counter.

The 4-digit decimal counter can be implemented using 4 counters with proper reset logic and some other logic that provides the enable signal for all of the counters at the proper time.

The controller can be designed using state diagram, and code it behaviorally in Verilog.

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