Decoder circuits receive inputs in the form of an N-bit binary number and generate one or more outputs according to some requirement. Decoding is the conversion of the N-bit binary number into M-bit output code so that each valid input creates a unique output code. Decoder inputs are typically viewed as a binary number representing some encoded quantity, and outputs typically drive some other circuit or device based on decoding that quantity. For example, a PS/2 keyboard decoder decodes the “scan codes” that are generated each time a given key is pressed (scan codes are unique binary numbers that are assigned to individual keys on a PS/2 keyboard). Most scan codes are simply sent to the host computer for parsing, but some perform specific functions. If the “caps lock” key is pressed, a signal is generated to illuminate an LED on the keyboard, and if “Ctrl-Alt-Del” is pressed, a signal is generated to interrupt PC operations.
Here, we will examine two different types of decoders—a simple binary decoder, and a seven-segment decoder (section 6.4) that can drive a common numeric data display.
A binary decoder has N inputs and 2N outputs. It receives N inputs (often grouped as a binary number on a bus) and then asserts one, and only one, of its 2N outputs based on that input. If the N inputs are taken as an N-bit binary number, then only the output that corresponds to the input binary number is asserted. For example, if a binary 5 (or “101”) is input to a 3:8 decoder, then only the 5th output of the decoder will be asserted and all other outputs will be de-asserted. Practical decoder circuits are usually built as 2:4 decoders with 2 inputs and 22 (4) outputs, 3:8 decoders with 3 inputs and 23 (8) outputs, or 4:16 decoders with 4 inputs 24 (16) outputs. A decoder circuit requires one AND gate to drive each output, and each AND gate decodes a particular binary number. For example, a 3:8 decoder requires 8 AND gates, with the first AND gate having inputs A'• B'• C', the second A' • B'• C, the third A'• B • C', etc. Figure 1 below displays a 3:8 binary decoder.
If a binary decoder larger than 4:16 is needed, it can be built from smaller decoders. Only decoders with an enable input can be used to construct larger decoder circuits. As with the mux, the enable input drives all outputs to '0' when de-asserted, and allows normal decoder operation when asserted.
Decoders are most often used in more complex digital systems to access a particular memory location based on an “address” produced by a computing device. In this application, the address represents the coded data inputs, and the outputs are the particular memory element select signals. A typical memory circuit contains a decoder to select which memory element to write, the memory elements themselves, and a mux to select which element to read.
As with multiplexers, this most common application of decoders is beyond our current presentation, so instead we will consider a less common, somewhat contrived application. Consider the function of a decoder and the truth table, K-map, or minterm representation of a given function. Each row in a truth table, each cell in a K-map, or each minterm number in an equation represents a particular combination of inputs. Each output of a decoder is uniquely asserted for a particular combination of inputs. Thus, if the inputs to a given logic function are connected to the inputs of a decoder, and those same inputs are used as K-map input logic variables, then a direct one-to- one mapping is created between the K-map cells and the decoder outputs. It follows that any given function represented in a truth table or K-map can be directly implemented using a decoder, by simply by OR'ing the decoder outputs that correspond to a truth table row or K-map cell containing a '1' (decoder outputs that correspond to K-map cells that contain a zero are simply left unconnected). In such a circuit, any input combination with a '1' in the corresponding truth table row or K-map cell will drive the output OR gate to a '1', and any input combination with a '0' in the corresponding K-map cell will allow the OR gate to output a '0'. Note that when a decoder is used to implement a circuit directly from a truth table or K-map, no logic minimization is performed. Using a decoder in this fashion saves time, but usually results in a less efficient implementation (here again, a logic synthesizer would remove the inefficiencies before such a circuit was implemented in a programmable device).
Our use of the word “multiplexer” has its origins in telecommunications, defining a system where one signal is used to transmit many different messages, either simultaneously or at different times. “Time-multiplexing” describes a system where different messages use the same physical signal, with different messages being sent at different times. Time-multiplexing works if a given signal can carry more traffic than any one message needs. For example, if ten messages each require that 1 Kbit of information be sent every second, and if a communication signal is available that can carry 10 Kbits per second, then time-multiplexing can be used to provide ten 1 Kbit time windows each second, one for each signal. A multiplexer can be used as a simple time-multiplexer if the select inputs are used to define the time window and the data inputs are used as the data sources.
A decoder with an enable can be used as a de-multiplexer, whereas a multiplexer selects one on N input to pass through to the output, a de-multiplexer takes a single input and routes it to one of N outputs. Figure 2 above illustrates the decoder with enable as a de-multiplexer. A multiplexer/de-multiplexer (or more simply, mux/de-mux) circuit can be used to transmit the state of N signals from one place to another using only Log2N+1 signals. Log2N signals are used to select the data input for the mux and to drive the decoder inputs, and the rate at which these signals change define the time-window length. The data-out of the mux drives the enable-in of the decoder, so that the same logic levels that appear on the mux inputs also appear on the corresponding decoder outputs, but only for the mux input/decoder output currently selected. In this way, the state of N signals can be sent from one place to another using only Log2N+1 signals, but only one signal at a time is valid.