Delay of Combinational Circuits

Propagation Delays

Electronic signals travel along conductors at about 8cm per nanosecond (the actual speed depends on the conductor material, dimensions, and other external factors). Electronic switches, like the field-effect transistors (FETs) used in logic circuits, typically require up to several hundred picoseconds to turn on and off. When a switch does turn on, it must transfer charge to or from the capacitance at its output node, and again, this takes time. All of these factors contribute to the simple fact that time is required for electric signals to propagate through logic circuits. Restated, time is required to process information in digital circuits. This processing time is divided between the less significant signal transmission time, and the more significant propagation delays associated with switching logic circuits. If not managed properly, propagation delays can result in logic circuits that run too slowly to meet their requirements, or that fail altogether.

A simple logic circuit, its equivalent CMOS circuit, and a timing diagram are shown below in Fig. 1 with a particular intra-gate node (N1) highlighted. The timing diagram illustrates logical behavior of signals as a function of time. Note that if B changes from low to high when C is high as shown, the circuit node N1 changes from high to low after a time $\tau_1$ has elapsed. The time $\tau_1$ is the “propagation delay” associated with the NAND gate. Referring to the CMOS circuit, the propagation delay $\tau_1$ models transistor Q1 turning on and discharging node N1 from Vdd to GND. Although there is no actual capacitor at the output node, all of the signal wires and FET connections associated with the circuit node N1 behave like a single capacitor, and this “parasitic” accumulated capacitance is shown lumped into a single component labeled C1. As is the case with any capacitor, C1 cannot transition from Vdd to GND immediately; the propagation delay $\tau_1$ models the time required to discharge this capacitance.

As the C1 capacitance discharges, the voltage at N1 decreases below the input switching threshold of the inverter, the inverter drives its output Y to a '1' after the propagation delay $\tau_3$. The propagation delay of the OR gate ($\tau_2$) is longer than the delay for the inverter—in general, different gates will have different propagation delays. Further, since the delay through a given gate depends on the number of other gates and wires that it must drive, different instances of the same type of gate in a given circuit will have different propagation delays as well. In a given digital circuit, a designer is typically interested in the system response time rather than individual gate delays. For this circuit, the system response times TBX and TBY that show the time required for signals X and Y to change in response to a change on signal B are shown at the bottom of the timing diagram.

The amount of time required to drive an output from '0' to '1' (or vice-versa) depends on how much capacitance is present on the output node. In a CMOS circuit, the capacitance on a given output node is determined by how many “downstream” gate inputs are connected to the output node (for example, in the circuit above, node A is driving a single gate input while node N1 is driving two gate inputs). As a first approximation, it is reasonable to assume a linear relationship between the number of downstream gates driven by an output node and the amount of time required to transition the output node. That is, if an output node connected to 2 downstream gate inputs can transition from '0' to '1' in time X, the same gate driving 4 downstream gate inputs can transition in time 2X.

Different circuit implementation technologies have different typical delays. For example, a circuit implemented in a modern FPGA will typically have delays that are much smaller than a circuit implemented in a five-year-old FPGA, and in turn, both FPGA circuits would have far smaller delays than a similar circuit built from discrete gates. The smallest delay times (on the order of 10's of picoseconds) are available in the most expensive technologies, and these are reserved for “fully custom” chip designs that sell in high-volumes (like Pentium processors), or for designs that require the best performance for specialized applications (like sensitive scientific instruments). Whatever the technology, circuit delays are affected by variations in the manufacturing process, so no two devices from the same manufacturing line will exhibit exactly the same delay. Further, delays can change when circuits are exposed to different operating environments—both temperature and power supply voltage can greatly alter delays on various circuit nodes.

When a design is “implemented” (i.e., translated and mapped to a given technology) in a CAD tool like Xilinx's® ISE/Webpack, a separate database containing specific information about every component in the design is created. This database contains information that defines the input/output relationships for each component, including the time required for input signal changes to propagate through the component to cause output signal changes. Delay information is typically stored separately for rising-edge transitions (i.e., a 0-to-1 transition) and for falling-edge transitions. Different delay values are used for rising and falling edges to account for the differences in the FETs that are used to drive an output node to '0' or '1'. In a falling transition, nFETs are responsible for driving the output node to '0', while in a rising transition, pFETs are responsible for driving an output node to '1' (see the circuit example above). In CMOS circuits, nFETs can typically pass twice the amount of current as similarly sized pFETs, so driving an output node to '1' typically takes twice as long as driving an output to '0'. Some simpler CAD tools ignore this phenomenon, and use a single number to define “gate delay”. This single gate delay number is applied to all inputs for both rising and falling transitions.

In general, the delays encountered in a given circuit cannot be precisely known until the circuit is transformed into its most basic structural representation. The most basic representation depends on the technology that will be used to implement the circuit. When circuits are synthesized to a given device like an FPGA or CPLD, all the “logical” components and interconnections specified in the source file are mapped to particular physical devices in the chip. Once this mapping happens, it is possible to calculate the delays for every circuit node in the design with a high degree of accuracy. Prior to this mapping, it is only possible to estimate the delays. Whether calculated or estimated, all useful logic simulators must accommodate delay values so that designers can simulate the behavior of physical circuits. In fact, it is fair to say that accurate delay modeling is the most important and most useful feature of a simulator. Designers have learned that they must know the effects of all delays on all circuit nodes prior to releasing a design to manufacturing.

In a modern design flow, a circuit is initially designed without paying much attention to delays. In this early stage, a simulator is used only to check that the circuit logic has been correctly defined. When the design is synthesized to a given technology, the CAD tools can automatically calculate accurate delays for every single circuit node. Then, the circuit can be re-simulated, and the designer can study the circuit's behavior with accurate node delays included. Delay information is typically stored in a file called a “standard delay format”, or .sdf file. In a post-synthesis simulation, the .sdf file is used by the simulator along with the circuit definition and the stimulus file to create a highly accurate output.

Many schematic-based CAD tools allow designers to include delays at the time a circuit is initially specified. These delays are by definition “best guesses”, but they are nevertheless useful in studying a given circuit's performance. These delay values can easily be modified to simulate a circuit's behavior under different operating conditions that might arise. For example, best-case or worst-case delays could be used to model circuit performance at different operating temperatures or supply voltages.

In problems and exercises up to this point, the focus has been on creating functionally correct circuits, and the effects of gate delays have been ignored. Going forward, you will come to appreciate that creating a “functionally correct” circuit is the simplest part of solving a given problem. The greater challenge often lies in creating a circuit that will always work in a given physical environment, with all the attendant gate delay and timing issues, and in validating circuit performance through testing.

Important Ideas

• The propagation delay of a signal path is the time it takes between the change in input and the change in output for that signal.
• If not managed properly, propagation delays can result in logic circuits that run too slowly to meet their requirements, or that fail altogether.
• The timing diagram illustrates logical behavior of signals as a function of time.
• The amount of time required to drive an output from '0' to '1' (or vice-versa) depends on how much capacitance is present on the output node.
• Different circuit implementation technologies have different typical delays.
• When a design is “implemented” (i.e., translated and mapped to a given technology) in a CAD tool like Xilinx's ISE/Webpack, a separate database containing specific information about every component in the design is created.
• Delay information is typically stored separately for rising-edge transitions (i.e., a 0-to-1 transition) and for falling-edge transitions. Different delay values are used for rising and falling edges to account for the differences in the FETs that are used to drive an output node to '0' or '1'.
• When the design is synthesized to a given technology, the CAD tools can automatically calculate accurate delays for every single circuit node.