Introduction to CMOS Technology

Logic Circuits Built from FETs

Introduction to CMOS Technology

Logic Circuits Built from FETs

Logic Gates in Complementary MOSFET Technology

Armed with the basic understanding of FET operation as described in previous sections, it is possible to construct a basic logic circuit that forms the back bone of all digital and computer circuits. These logic circuits will combine one or more input signals to produce an output signal according to the logic function requirements. The following discussion is restricted to circuits for basic logic functions (like AND, OR, and INV), but FET circuits can readily be built for more complex logic circuits as well.

When building FET circuits to implement logic relationships, four basic rules must be followed:

  1. pFET sources must be connected to Vdd and nFET sources must be connected to GND.
  2. The circuit output must always be connected to Vdd via an on pFET or to GND via an on nFET (i.e., the circuit output must never be left floating).
  3. The logic circuit output must never be connected to both Vdd and GND at the same time (i.e., the circuit output must not be “shorted”).
  4. The circuit must use the fewest possible number of FETs.

Following these rules, a circuit that can form the AND relationship between two input signals is developed. But first, note that in the circuit on the right in Fig. 1, the output (labeled Y) is connected to GND only if the two inputs A and B are at Vdd. The two nFETs labeled Q1 and Q2 are said to be in series; in general, a series connection of FETs is required for an AND function. In the circuit in Fig. 1 below, the output Y is connected to GND if A or B are at Vdd. The two nFETs labeled Q3 and Q4 are said to be in parallel; in general, a parallel connection of FETs is required for an OR function.

Figure 1. nFETs serial and parallel configuration.

Keeping in mind the rules for FET logic circuits, an AND structure is created from Q1 and Q2 below. Using just these two FETs, Y is driven to GND whenever A and B are at Vdd. But we must also ensure the output Y is at Vdd when A and B are not both at Vdd; restated, we must ensure the output Y is at Vdd whenever A or B are at GND. This can be accomplished with an OR'ing structure of pFETs (Q3 and Q4 below). The AND'ing structure and OR'ing structure are assembled in the circuit on the right in Fig. 2 below. The adjacent operation table shows the input and output voltages for all four possible combinations of inputs. Note that this circuit obeys all of the rules above—pFETs are connected only to Vdd, nFETs are connected only to ground, the output is always driven to Vdd or to GND but never to both simultaneously, and the fewest possible number of FETs are used.

Figure 2. NAND gate configurations and table.

This AND'ing circuit has the interesting property of producing an output signal at GND when both inputs A and B are at Vdd. In order to have this circuit's performance match the AND logical truth table above, we must associate an input signal at Vdd with a logic 1 (and therefore, an input signal at GND must be associated with a logic 0); and we must associate an output signal at GND with a logic '1'. This creates a potentially confusing situation—considering the '1' symbol to represent a signal at Vdd on the input of a gate, and then considering that same '1' symbol to represent a signal at GND on the output of a gate. Note that if the outputs in the Y column of the truth table were inverted (that is, if Vdd were changed to GND and GND were changed to Vdd), then a '1' symbol could represent Vdd for both the inputs and outputs, resulting in the AND truth table presented earlier. Because of this, the circuit shown above is called a NOT AND gate (were NOT means inversion), which is shortened to “NAND” gate. To create an AND circuit in which both the input signals and output signals can associate a Vdd signal with a logic '1', an inverter circuit must be added to the output of the NAND gate (as the name implies, an inverter produces a Vdd output for a GND input, and vice-versa). An NAND gate produces a GND output only when all the inputs are Vdd.

Figure 3. Generic CMOS topology.

Shown in Fig. 4 below are the five basic logic circuits: NAND, NOR (for NOT OR), AND, OR and INV (for inverter). The reader should verify that all truth tables show the correct circuit operation. These basic logic circuits are frequently referred to as logic gates.

Figure 4. Basic CMOS gates and their truth tables.

In each of these logic gates, a minimum number of FETs has been used to produce the required logic function. Each circuit has nFETs “on the bottom” and pFETs “on the top” performing complementary operations; that is, when an OR relationship is present in the nFETs, an AND relationship is present in the pFETs. FET circuits that exhibit this complementary nature are called Complementary Metal Oxide Semiconductor, or CMOS circuits. CMOS circuits are by far the dominant circuits used today in digital and computer circuits. (Incidentally, the Metal-Oxide-Semiconductor name refers to older technologies where the gate material was made of metal and the insulator beneath the gate made of silicon oxide). These basic logic circuits form the basis for all digital and computer circuits.

When these circuits are used in schematic drawings, the well-known symbols shown below in Fig. 5 are used rather than the FET circuit diagrams (it would simply be too tedious to draw the FET circuits). A straight edge on the input side of a symbol and smoothly curved output side means AND, while a curved edge on the input side and pointed output side means OR. A bubble on an input means that input must be at LLV to produce the indicated logic function output, and a bubble on the output means that a LLV output signal is produced as a result of the logic function. The lack of a bubble on inputs means that signals must be at LHV to produce the indicated function, and the lack of a bubble on the output means that a LHV signal is produced as a result of the logic function.

Figure 5. Logic gate symbols.

Note that each of the symbols above has two appearances. The symbols on the top may be considered the primary symbols, and those on the bottom may be considered the conjugate symbols (properly, each symbol is the conjugate of the other). Conjugate symbols swap AND and OR shapes, and input and output assertion levels. The reader should verify that both symbols are appropriate for the underlying CMOS circuit. For example, the AND shaped symbol for the NAND circuit shows that if two inputs A and B are at LVH, then the output is at LLV. The OR shaped symbol for the NAND circuit shows that if either of the two inputs A and B are at LLV, then the output is at LHV. Both statements are true, illustrating that any logic gate can be thought of in conjugate forms. (Why conjugate forms? In certain settings, it can be easier for humans to follow circuit schematics if the appropriate symbol is used—more on this later).

Important Ideas

  • FET logic circuits will combine one or more input signals to produce an output signal according to the logic function requirements. Although we confined the FET logic circuits to the AND, OR, and NOT functions, they can easily be applied to more complex circuits.
  • The five basic logic circuits are frequently referred to as logic gates.
  • In each of these logic gates, a minimum number of FETs has been used to produce the required logic function. Each circuit has nFETs “on the bottom” and pFETs “on the top” performing complementary operations; that is, when an OR relationship is present in the nFETs, an AND relationship is present in the pFETs. FET circuits that exhibit this complementary nature are called Complementary Metal Oxide Semiconductor (CMOS) circuits.
  • When these circuits are used in schematic drawings, the well-known symbols are used rather than the FET circuit diagrams (it would simply be too tedious to draw the FET circuits). A straight edge on the input side of a symbol and smoothly curved output side means AND, while a curved edge on the input side and pointed output side means OR.

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