Logic Minimization

Project 4, Exercise 1

Project 4, Exercise 1:

Logic Minimization


This Exercise is based on the material covered in Real Digital Project 4, which can be found in the red tab to the right. A downloadable document for this exercise is available in the orange tab to the right. The mention of grading within the downloadable document is due to the exercise material being used as course work for an electrical engineering class at a university.

Before beginning this exercise, you should…
  • Be familiar with reading and constructing basic logic circuits.
  • Understand logic equations, and how to implement a logic circuit from a logic equation.
  • Know how to operate Windows computers and Windows programs.
After completing this exercise, you should…
  • Be able to minimize any given logic system.
  • Understand CAD tool use in basic circuit design.
  • Be able to implement any given combinational circuit using the Xilinx ISE schematic editor.
  • Be able to simulate any logic circuit.
  • Be able to examine the output of a logic simulator to verify whether a given circuit has been designed correctly.
This exercise requires:
  • A Windows PC running the Xilinx ISE/WebPack software.
  • The Xilinx® ISE®/WebPACK™ software.
  • A Digilent circuit board.

Problem 1.

Show the total transistor count and gate/input number for the circuits below. Then sketch equivalent circuits that use fewer transistors (hint: NAND)

Problem 2.

Find minimal equations for the systems shown.

Problem 3.

Find minimal equations for the systems shown below. Circle the equation of the simplest form (SOP or POS), and circle both if they are equal.

Problem 4.

Find minimal SOP and POS equations for the systems shown.

Problem 5.

Find minimal SOP and POS equations for the systems shown.

Problem 6.

Find global minimum circuits for the following three logic signal outputs that are all functions of the same three inputs. Show all work

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