 # Project 6, Exercise 1

## Overview

This Exercise is based on the material covered in Real Digital Project 6, which can be found in the red tab to the right. A downloadable document for this exercise is available in the orange tab to the right. The mention of grading within the downloadable document is due to the exercise material being used as course work for an electrical engineering class at a university.

##### Before beginning this exercise, you should…
• Be able to specify, design, and minimuze combinational logic systems.
• Be able to create schematic-based or VHDL-based designs in the Xilinx® WebPACK™ environment.
• Be able to download design created in WebPACK to the Digilent Circuit Board.
##### After completing this exercise, you should…
• Understand the application, function, and structure of decoder, multiplexor, encoder, and shifter circuits.
• Know how to use these circuits in the solution of larger problems.
• Be able to implement any given combinational circuit using the Xilinx CAD tool environment.
##### This exercise requires:
• A windows computer running Xilinx WebPACK.
• A Digilent board.

#### Problem 1.

Complete the 4:1 mux circuit by sketching the missing wires.

#### Problem 2.

Complete the truth table and circuit sketch for a 4:1 mux. When completing the truth table, make use of don't cares to reduce the number of required rows.

#### Problem 3.

Sketch an 8:1 mux using two 4:1 muxes and one 2:1 mux. Be sure to label all inputs and outputs.

#### Problem 4.

Complete a circuit sketch to show how F = Σm(0, 2, 4, 5, 6) can be implemented using the mux shown. (Hint: prepare an entered-variable K-map).

#### Problem 5.

Complete the 3:8 decoder schematic by sketching the missing wires.

#### Problem 6.

Complete the 3:8 decoder with enable schematic by sketching the missing wires.

#### Problem 7.

Complete the 4:16 decoder built from 4 2:4 decoders below by sketching the missing wires. Label all inputs and outputs.

#### Problem 8.

Complete a sketch to show how the 3:8 decoder can be used to implement the logic equation F = Σm(1, 2, 4, 6)

Decoder inputs and outputs are all asserted HIGH.

#### Problem 9.

Complete the truth table. The table shows the nine decimal digits, their binary equivalents, and seven columns labeled A-G. The columns labeled A-G can be used to record when a segment must be illuminated to display a given digit. For example, in the first row corresponding to the digit '0', segments A, B, C, D, E, and F must be illuminated, so a '1' must be placed in those columns. When completed, the table can serve as a truth table for the seven-segment controller—it shows the required logic relationship between the four inputs and seven outputs. Note that in the truth table, the last six input patterns (1010 through 1111) are not associated with a decimal digit. They are therefore “illegal” inputs, so outputs can receive a “don't care” for those rows.

#### Problem 10.

Complete the truth table for a three-input priority encoder. When completing the truth table, note that if I3 is a '1', it DOES NOT matter what I2, I1, or I0 are—the encoded output will be “11”. This information can result in don't cares in the truth table, which makes the design much easier (note that X's have been used in the truth table to indicate don't care input conditions). When the truth table is complete, write VHDL equations to define the encoder circuits.

#### Problem 11.

Complete the truth table for a 4-bit shifter that has no enable input, no rotate input, two inputs that dictate whether the input is to be shifted 0, 1, 2, or 3 bits, a direction input, and a fill input.

#### Problem 12.

Complete the table below to show the numerical results from applying the indicated operation to the data shown. Opcodes are six-bit numbers defined as shown below. R = 1 for Rotate; D = 1 for Right; F is fill, and A2-A0 define the number of bits. Show all work.