Combinational Arithmetic Circuits

Project 7, Exercise 1

Project 7, Exercise 1

Combinational Arithmetic Circuits


This Exercise is based on the material covered in Real Digital Project 7, which can be found in the red tab to the right. A downloadable document for this exercise is available in the orange tab to the right. The mention of grading within the downloadable document is due to the exercise material being used as course work for an electrical engineering class at a university.

Before beginning this exercise, you should…
  • Be able to add, subtract, and multiply binary numbers.
  • Be able to enter and simulate circuits using schematic and VHDL methods in the Xilinx® ISE®/WebPACK™ tool.
  • Be able to download circuits to the Digilent board.
  • Be familiar with design of basic combinational circuit blocks.
After completing this exercise, you should…
  • Know how to design circuits using structural VHDL methods.
  • Know how to use these circuits in the solution of larger problems.
  • Know when and how to apply the bit-slice design method.
  • Understand how comparators, adders, subtractors, and multipliers work, and be able to design them using schematics or VHDL.
This exercise requires:
  • A windows computer running Xilinx WebPACK tools.
  • A Digilent circuit board.

Problem 1.

Sketch a block diagram for a magnitude comparator bit-slice circuit. Create K-maps to define the bit-slice circuit, and use them to find optimal logic equations. Sketch the circuit.

Problem 2.

Modify the block diagram and circuit of problem 1 by removing the logic gates and signals that form the EQ output. Sketch a circuit diagram for a 4-bit comparator that uses the modified bit slice blocks, and add a single gate to form the EQ output from the LT and GT outputs from the MSB (most significant bit). Comment on the differences in the new circuit (i.e., which circuit is more efficient? Which is easier to design and implement? Which might run faster? Anything else?)

Could you make the bit-slice modules even more efficient by leaving in the EQ logic and removing some other logic? Explain.

Problem 3.

Complete truth tables and K-maps for HA and FA circuits, using XOR patterns where appropriate. Loop minimum SOP equations, and sketch the circuits (assume all inputs and outputs are active high).

Problem 4.

Sketch a circuit for a full adder using two half-adder blocks and an OR gate.

Problem 5.

Complete the truth table and K-maps for a CLA adder bit-slice module, and sketch a minimal SOP circuit (be sure to use XOR's where appropriate!).

Problem 6.

Sketch a Carry-Propagate-Generate circuit that can form the carry-ins for a 4-bit CLA.

Problem 7.

Design a full-subtractor bit-slice circuit. Label the inputs A, B, and Bin, and label the outputs D and Bout. Start by completing the subtraction examples, then complete the truth table and K-maps, and then sketch the circuit.

Problem 8.

Complete the number conversions indicated. Note that all binary numbers are two's complement representations.

Problem 9.

Complete the four 2's compliment arithmetic problems below, showing both the decimal and binary numbers in each case.

Problem 10.

Sketch a circuit to convert a 4-bit binary number to its 2's complement representation. (Hint: can you use only 3 XOR/XNOR gates and 2 AND or OR gates?).

Problem 11.

Explain how the circuit structures of a ripple-carry adder circuit configured as a 2's compliment subtractor and a ripple-borrow subtractor perform identical functions.

Problem 12.

Examine several examples of addition overflow and subtraction underflow, and sketch a circuit below that can output a '1' whenever an addition or subtraction result is incorrect due to underflow or overflow. (Hint: compare the carry-in and carry-out signals of the most-significant bit).

Problem 13.

Fill in the squares below to show all signal values when “1101” and “1010” are multiplied.

Problem 14.

Sketch a block diagram for a 4-bit ALU built from bit-slice ALU circuits that can implement the functions shown in the table. Label all signals, and recall that inputs to the bit slices must come from the A and B input busses as well as from neighboring bit slices (and outputs must drive the F output bus as well as neighboring bit slices). To design the signals that communicate information between slices, you must understand the ALU operations and the implications for information transfer (e.g., does the operation A PLUS B require that information be transferred between slices? If so, what? Does the operation A OR B require that information be transferred?).

Problem 15.

In the ALU example in the module it was stated that an 8:1 mux could be use for the F output and a 4:1 mux could be used for the Cout output. Sketch the mux-based circuit.

Problem 16.

Transfer the ALU operation table from the module has been reproduced below, but opcode 3 has been redefined as “decrement”. Complete the F and Cout table entries to define the decrement logic functions.

Problem 17.

Write VHDL statements to define the ALU's operation.

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