 # Project 8, Exercise 1

## Overview

This Exercise is based on the material covered in Real Digital Project 8, which can be found in the red tab to the right. A downloadable document for this exercise is available in the orange tab to the right. The mention of grading within the downloadable document is due to the exercise material being used as course work for an electrical engineering class at a university.

##### Before beginning this exercise, you should…
• Be familiar with combinational logic circuits of all sorts, from basic SOP and POS circuits through more complex arithmetic and logic designs.
• Be able to design and simulate structural and behavioral circuits using VHDL and/or schematic capture in the Xilinx® ISE®/WebPACK™.
• Be familiar arithmetic circuits and the bit-slice design method.
##### After completing this exercise, you should…
• Understand where circuit delays come from.
• Be able to analyze a combinational circuit to determine whether its outputs will suffer from logic noise (or “glitches”).
• Use the Xilinx tools to modify circuit delays and analyze their affects.
##### This exercise requires:
• A windows computer running the Xilinx ISE/WebPack tools.

#### Problem 1.

Implement the function Y = A'·B + A·C in the VHDL tool. Define the INV, OR and two AND operations separately, and give each operation a 1ns delay. Simulate the circuit with all possible combinations of inputs. Watch all circuit nets (inputs, outputs, and intermediate nets) during the simulation. Answer the questions below.

Observe the outputs of the AND gates and the overall circuit output when B and C are both high, and A transitions from H to L and then from L to H (you may want to create another simulation to focus on this behavior). What output behavior do you notice when A transitions?

What happens when A transitions and B or C are held a '0'?

How long is the output glitch? Is it positive ( ) or negative ( )?

Change the delay through the inverter to 2ns, and resimulate. Now how long is output glitch?

What can you say about the relationship between the inverter gate delay and the length of the timing glitch?

Based on this simple experiment, an SOP circuit can exhibit positive/negative glitches (circle one) when an input that arrives at one AND gate in a complemented form and another AND gate in uncomplemented form transitions from a _____ to a _____.

#### Problem 2.

Enter the logic equation from problem 1 in the K-map below, and loop the equation with redundant term included. Add the redundant term to the Xilinx circuit, re-simulate, and answer the questions.

Did adding the new gate to the circuit change the logical behavior of the circuit?

What effect did the new gate have on the output, particularly when A changes and B and C are both held high?

#### Problem 3.

Create a three-input POS circuit to illustrate the formation of a glitch. Drive the simulator to illustrate a glitch in the POS circuit, and answer the questions below.

A POS circuit can exhibit a positive/negative glitch (circle one) when an input that arrives at one OR gate in a complemented form and another OR gate in un-complemented form transitions from a _____ to a _____.

Write the POS equation you used to show the glitch:

Enter the equation in the K-map below, loop the original equation with the redudant term, add the redundant gate to your Xilinx circuit, and resimulate.

How did adding the new gate to the circuit change the logical behavior of the circuit?

What effect did the new gate have on the output, particularly when A changes and B and C are both held high?

Print and submit the circuits and simulation output, label the output glitches in the simulation output, and draw arrows on the simulation output between the events that caused the glitches (i.e., a transition in an input signal) and the glitches themselves.

#### Problem 4.

Copy the SOP circuit above to a new VHDL file, and increase the delay of the output OR gate. Simulate the circuit and answer the questions below.

How did adding delay to the output gate change the output transition?

Does adding delay to the output gate change the circuit's glitch behavior in any way?

#### Problem 5.

Create a circuit for Z = (A·B) · (A·C)'. Change the delay of the AND gate to 1ns and the NAND gate to 2ns. Simulate the circuit, inspect the output, and answer the question below.

What kind of glitch did you observe?

What input conditions are required for the glitch to form?

How long was the glitch, and how is its length related to timing delays in the AND and NAND gates?

Print and submit the circuits and simulation output, label the output glitches in the simulation output, and draw arrows on the simulation output between the events that caused the glitches (i.e., a transition in an input signal) and the glitches themselves.

#### Problem 6.

Design and implement an 8-bit adder using behavioral VHDL. Use a VHDL test-bench to simulate the circuit in post-route mode, have the Lab Assistant inspect your simulation output, and print and submit the source and simulation files. Annotate the simulation output to show the “settling” time of the adder (i.e., the time the outputs are in flux).

How long does it take for the adder result to be valid after the inputs change?

What is maximum frequency this circuit could run at?

#### Problem 7.

Simulate your 8-bit RCA and CLA from the previous exercise in post-route mode using the test bench from problem 6 above. Print and submit the source file and simulation outputs. Annotate the simulation outputs to show the “settling” time of the adders. How long does it take for the adder results of each to be valid after the inputs change?

## Appendix 1. Running the ISE/WebPACK Simulator in the Post-Route Mode

To run the simulator in the post-route simulation mode, choose “post-route simulation” from the “Sources for:” pull-down menu in the Source window of the project navigator, and run the simulator as before (note the only process available in the “Processes” window is “Simulate Post-Place & Route Model”). The figure below shows a screenshot with the appropriate choices highlighted.