Overview

This Exercise is based on the material covered in Real Digital Project 9, which can be found in the red tab to the right. A downloadable document for this exercise is available in the orange tab to the right. The mention of grading within the downloadable document is due to the exercise material being used as course work for an electrical engineering class at a university.

Problem 1.

Create a NAND basic cell in the Xilinx Tools using structural VHDL methods. Add a 1ns gate delay to both NAND gates (for both rising and falling transitions). Label inputs S and R and the outputs Q and QN as appropriate. Create a VHDL test bench to simulate the circuit, driving the inputs as specified below. Print the waveform output from the simulator, and annotate it with a pen or pencil to indicate the output features in the list below.

De-assert both inputs at the start of the simulation. At 100ns, asset S. At 200ns, de-assert S. At 300ns, assert R. At 400ns, de-assert R. At 500ns, assert both inputs. At 600ns, de-assert both inputs. At 700ns, assert both inputs.

1. An undefined output
2. A set operation
3. A reset operation
4. A '0' being stored in memory
5. A '1' being stored in memory
6. A state where the Q and QN outputs are both driven to the same value
7. A metastable state

Problem 2.

Repeat problem 1, but use a NOR basic cell. Why are the basic cells outputs undefined at the start of the simulation?

Complete the following table by placing the correct letter in the output column: A: set operation; B: reset operation; C: confounded outputs (both outputs at the same voltage); D: storing a value in memory; E: a metastable state.

Problem 3.

Modify the test bench for the NAND basic cell by de-asserting S at 600ns and R at 601ns, and resimulate. Comment on any differences in the output, and more importantly, give a reason for any differences seen.

Problem 4.

Starting with the NAND basic cell, create a new source file for a D-latch. Be sure the basic cell NAND gates have a 1ns gate delay. Create and run a VHDL test bench to simulate this circuit, and be sure to test all possible combinations of inputs to fully document the circuit's function. At some point during the simulation, illustrate the property of D-latch transparency (i.e., show the circuit behavior when gate input is high, and the D input changes from L-H-L or H-L-H), and also illustrate a metastable state. Mark on a printout of the simulation waveform the following output behaviors: an undefined output, transparency, storing a '1', storing a '0', and metastability.

Problem 5.

Create a behavioral source file for a RET DFF. Name the inputs D and CLK, and the output Q. Create a VHDL test bench to simulate the flip-flop, driving CLK and D appropriately. What do you notice about the output Q? Why?

Add an asynchronous reset, and assert the reset signal at the start of the simulation, de-asserting it after a small amount of time. Resimulate, and demonstrate the proper operation of your flip-flop.

Modify the simulation, and try to force a metastable state. Can you force a metastable state? Print and submit your source file, and a single simulation file showing proper flip-flop operation and your attempt to get it into a metastable state.

Problem 6.

Create a source file for a FET DFF with clock enable and preset. Simulate the FF, showing all pertinent operating states.

Problem 7.

Create a source file for an 8-bit D register with both a synchronous reset (named SRST) and an asynchronous reset (named ARST). Simulate the register, showing all pertinent operating states.

Problem 8.

Create and simulate a source file for a T flip-flop. Show all pertinent operating states in the simulation.

Problem 9.

Create and simulate a source file for a JK flip-flop. Show all pertinent operating states in the simulation.