This Exercise is based on the material covered in Real Digital Project 10, which can be found in the red tab to the right. A downloadable document for this exercise is available in the orange tab to the right. The mention of grading within the downloadable document is due to the exercise material being used as course work for an electrical engineering class at a university.
Using the Xilinx® CAD tools, create a structural 4-bit counter with CEN and TC functions. You may use schematic methods and the FDCE flip-flop component from the Xilinx library, or structural VHDL methods (in which case you can use the flip-flop you designed in the previous lab). To complete the design, you will need to find next-state logic circuits for the counter. A state diagram and K-maps have been provided below for this purpose (or, nothing is keeping you from “borrowing” a circuit from the Xilinx schematic library, but you must complete the K-maps regardless). When the counter is complete, simulate it using a VHDL a test bench file, and be sure to show all appropriate output states. (Hint: Extensive XOR patterns are present in the D next-state maps. You will probably want to refer to some circuit schematic source to check your K-map looping.)
Empty K-maps can be found below. Note that if you choose to design a counter using DFFs with a CE input, you can ignore the CEN inputs shown in the state diagram above (i.e., the state diagram would only show branches to the next state, without any holding conditions). In this case, the counter's CEN input would directly drive the CE inputs on the DFFs (this makes the K-map loading and looping a fair amount easier—but it is your choice!).
Create and simulate a behavioral VHDL 4-bit counter, using a VHDL test bench for the simulation.
Design a circuit that increments a digit (0 – F) shown on the seven-segment display device once each second. The circuit has four pushbutton inputs: one button starts the counter, a second button stops the counter, a third button increments the counter, and the fourth button asynchronously resets all memory devices in the design. The system has the block diagram shown below. You must create the 4-bit counter, a clock divider, a seven-segment display decoder, and a controller circuit. You may use any design tools or methods you wish. You must also create and submit a state diagram for the controller, together with K-maps showing the next-state and output circuits.
Modify your circuit so that all four digits on the seven-segment display are driven, and drive the least-significant digit so that it changes at a rate of once per millisecond (and so, the most-significant bit will change at a rate of once per second). This circuit requires a scanning display controller which is discussed in your board's Reference Manual. Also create a detailed block diagram of your circuit showing all circuit blocks and signal connections (and make sure to appropriately label all circuit blocks and signals).