Getting Started with FPGA

Vivado Project 1: Introduction to Vivado

Introduction

This project sets up your FPGA board for use with Xilinx® Vivado™ and shows you the steps in starting project files. It also gives basic background knowledge on electrical engineering using digital circuits. This is a starter project with very little hands-on work with your board, but it is a good reference if you ever forget how to start your projects.

Before you begin, you should:
  • Have a Digilent® FPGA board that works with Xilinx Vivado.
  • Have a PC with internet access.
  • Have some time to set up your board and download the tools for further projects.
After you're done, you should:
  • Have the Xilinx Vivado WebPACK™ installed.
  • Have a basic understanding of what digital engineering is.
  • Know how to set up a Verilog® project for your FPGA board.

Inventory:

Qty Description
1 Digilent Nexys™4, or Basys™3 FPGA Board
1 Xilinx Vivado Design Suite: WebPACK (2014.4 Recommended)
1 Digilent Adept

Basic Theory

The use of the word circuit in this context comes from the idea that electric power must flow from the positive terminal of a power source through one or more electronic devices and back to the negative terminal of a power source, thereby forming a completed circuit. If the connections between an electronic device and either the positive or negative terminals of a power supply are interrupted, the circuit will be broken and the device will not function.

A digital circuit consists of a power supply, devices, and conduction nets. Some nets provide circuit inputs from the “outside world”; in a schematic, these input nets are generally shown entering the left side of component and/or the overall circuit. Other nets present circuit outputs to the outside world; these nets are generally shown exiting the schematic on the right side. Circuit components are shown as arbitrary shapes, nets are shown as lines, and inputs and outputs are denoted by connector symbols.

In a digital circuit, power supply voltage levels are constrained to two distinct values – “logic high voltage” (called LHV or Vdd) and “logic low voltage” (called LLV or GND). The GND node in any circuit is the universal reference voltage against which all other voltages are measured (in modern digital circuits, GND is typically the lowest voltage in the circuit, making all other voltages positive). In a schematic, it is often difficult to show lines connecting all GND nodes; so any nodes labeled GND are assumed to be connected into the same node. The Vdd node in a digital circuit is typically the highest voltage, and all nodes labeled Vdd are tied together into the same node. Vdd may be thought of as the “source” of positive charges in a circuit, and GND may be thought of as the “source” of negative charges in a circuit. In modern digital systems, Vdd and GND are separated by anywhere from 1 to 5 volts. Older or inexpensive circuits typically use 5 volts, while newer circuits use 1-3 volts.

In digital circuits, the Vdd and GND voltages are used not only to supply electric power to circuit devices; they are used to represent information as well. The most basic digital devices are called gates. The function of gates, or“gating,” is to allow or halt the flow of digital information. In general, a gate has one or more inputs and produces an output (more on that later).

Now that you have a basic understanding of what digital engineering is and how the circuits function, let’s move on to setting up your FPGA board and get started.

Step 1: Download the Xilinx Vivado Standalone Webinstall Client

You will need to have a computer connected to the internet and some time for this step.

  1. Follow the link to install Xilinx Vivado WebPACK tools. All projects require a Xilinx Vivado Design Suite WebPACK Edition. The download covers all editions of the Vivado Design Suite, and you will be prompted later to select the correct license; the WebPACK license.

  2. Once the download and installation is complete, the license manager should open and prompt you to select which version of Vivado you want. Select the radio button for the WebPACK edition. Follow the prompts to receive and activate your license.

Step 2: Create a Vivado Project

This set of steps is for you to learn how to create a project. Once you can create the module for a Verilog project, you will have completed this exercise.

Select your board from the drop down box and download the file you need for this project:

  1. Open Vivado.

  2. NOTE: To open Vivado in Linux, use the commands in the image below.
  3. Click on Create New Project. This will open the new project wizard.

  4. The new project wizard will give you a summary of the information you will need. Click Next to continue creating your new project.


  5. On the first page:
    • Enter a name for the project, in this case project_1.1GettingStarted. I found that including both the project number and class project name in the project name was most helpful. That way when you need to reference the project later, you don't need to remember both what the project was and the project number.

      NOTE: it is recommended that the path of location and working directory does not contain white space. (i.e., C:\Document and Settings\... is not recommended as there are spaces in the path. Having white space in the file path might cause XST to fail.)
  6. Next, the project wizard will prompt you to choose source files for your project. If you had already created source files you can add them here by selecting Add Files. If you needed to create new source files, you can do that here by selecting Create File. However, you can also add them later outside of the New Project Wizard. I will show you how to add the source files later in the project. Click Next to continue.

  7. Select your project type. For this class we will use the project type RTL Project. Select the RTL Project radio button and hit Next.

  8. The wizard will prompt you to add an existing IP. An IP is an intellectual property, or an existing module. Vivado has a huge library of IPs that you can add to your designs. However, in this class we will build all of our projects from scratch. Click Next to continue.

  9. Next, the project wizard will prompt you to add a constraints file. The constraints file connects the nets from your project to physical pins on the board. However, we can add this file later. Click Next to Continue.

  10. The last bit of information that you need to enter is the details about the FPGA chip on your FPGA board. You will need to know the family, package, speed grade, and temperature grade of your FPGA chip. The figure below uses the Basys 3 as an example, and has each piece of information highlighted. NOTE: These details are also listed in the reference manual for each board.
    Below you can see the information for the Basys 3 selected in the project wizard. You may have to change the tab on the upper left corner to parts, as the Basys 3 is not an automatically loaded board.
  11. The final page of the wizard shows the project summary. Click Finish after you have looked over the details of your project.
  12. After the wizard finishes, you will be left with a blank window similar to the image below:
  13. Right-click on Design Sources in the Project Manager and select the option Add Sources...
  14. The Add Source window will open. Navigate to the boardname_p1 directory that you downloaded previously. Open “project0_boardname.v”.
  15. After adding the “ project0_boardname.v” file to the project, add the .xdc file from the directory to the project by right clicking on Constraints and following the same steps as above. You can examine both the Verilog file (file.v) and the XDC file (.xdc) by double-clicking the file in the sources tab in the project manager.
  16. Now that you have the Verilog file and the appropriate XDC file added to the project, you can build the project by double-clicking on Run Synthesis.
  17. Once the project is done running synthesis, it will prompt you for a next step. Continue on to the next step by selecting Run Implementation and clicking OK.
  18. Once the project is done running implementation, it will prompt you for a next step. Continue on to the next step by selecting Generate Bitstream and clicking OK.
  19. Once the project is done building the bit file, Vivado will prompt you to open the hardware manager. This means you have built the bit file and are ready to program your board!
  20. The above are screenshots of Xilinx Vivado WebPACK running on Windows 8.1.
  21. Now that we have a bit file generated from the Xilinx tools, it's time to program with the hardware manager!

Step 3: Setup Your FPGA Board and Program it With the Bit File

  1. Select Open Hardware Manager on the prompt from the previous step and select OK.

  2. Next, you will need to open a hardware target. Select Open a New Hardware Target, which is the blue text on the green bar on the top of the screen.
  3. Next, you need to select the hardware server. Since you will be connecting your board to your local machine, select Local Server and click Next.
  4. Now that the Hardware Manager knows where to look, it needs to know what to look for. The next screen will prompt you to select the hardware target. Your target should be highlighted in blue since you probably only have one Digilent device plugged in to your computer.
  5. The next screen will give you a summary of the hardware target. Review the information and select Finish.
  6. Next, you will need to program your board. Click on Program Device in the blue text on the green bar, and select your device.
  7. The program device window will appear. The correct bitstream file should already be selected, but double check to be sure.
  8. Click on Program and your board will be programmed. You will see the demo operating and showing the green LEDs on except for one LED that is off, and moving across the LEDs. The seven-segment display will change through the different segments. When this is complete you have finished this project!

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