Design Simple Logic Circuit

Vivado Project 3: Guess the Logic

Introduction

In this project, you will download a bit file to your board in order to configure the FPGA with four different logic circuits. The circuits use buttons and switches for inputs, and LEDs for outputs. You must probe the logic circuits by applying all possible combinations of input signals. From the results of applying all possible combinations, you will be able to write logic equations that describe the circuits' behaviors. You will then rewrite the equations using Verilog HDL, which will re-implement them on the FPGA and compare the circuit behavior with the given bit file.

Before you begin, you should:
  • Have the Xilinx® Vivado WebPACK™ installed.
  • Have your FPGA board set up.
  • Understand how to program your FPGA board.
  • Understand how to add a Verilog HDL file and write a XDC file.
After you're done, you should:
  • Define a logic circuit using truth tables.
  • Derive logic equations from truth tables.
  • Describe logic functions using Verilog HDL and implement them on an FPGA.

Inventory:

Qty Description
1 Digilent® Nexys™4, or Basys™3 FPGA Board
1 Xilinx Vivado Design Suite: WebPACK (2014.4 Recommended)

Truth Table and Logic Function

A truth table is the primary tool for capturing logical relationships in a concise and universally understood format. A truth table contains a column of each input on the left and one final column for the output on the right. The truth table contains all possible input and output configurations of any given logic equation. A two input AND logic operation is defined using the truth table below:

A B F
false false false
false true false
true false false
true true true

Zeros and Ones

A signal in a digital circuit is a circuit net that transports an output voltage from one device to one or more input connections of other devices. In a digital circuit, signals are constrained to be at one of two voltages, either Vdd (1) or GND (0). Thus, all data in digital circuits can only be represented as a zero or one for the two available states. Systems that use two-state data are known as binary systems, and a two-state signal is a binary signal. One signal wire in a digital circuit can carry one binary digit (abbreviated to bit) of information. Conventionally, we assign symbol “1” to true and “0” to false. For example, an AND relation can be logically described as “true” when all of the inputs are “true.” Using the binary numbers assigned to a digital system, the logical AND truth table appears below:

A B F
0 0 0
0 1 0
1 0 0
1 1 1

Step 1: Download Bit File to Your Board

  1. Click the download button to obtain the pre-compiled bit file:
    Choose your FPGA board:
  2. Program your FPGA board with the bit file using Xilinx Hardware Manager, as demonstrated in Project 1.

Step 2: Probe the logic circuit and fill out the truth table

There are four circuits implemented in the bit file that you downloaded in Step 1. You are going to start probing them one by one.

  1. Circuit 1

    The first circuit takes SW0 and SW1 as inputs and uses LD0 to indicate the output of the logic function. As there are two inputs for this logic circuit, there are four possible combinations. According to the circuit of the switch, when the switch slides on, a high voltage (i.e., a logic “1”) will be presented on the input of the circuit. Similarly, if the LD0 turns on, a high voltage is presented on the output of the circuit, which means the current output of the logic circuit is a logic “1”. So we have both SW0 and SW1 off and we will need to check the LD0 status to fill out the first line of the truth table below. Slide the SW0 on to fill out the second row. Slide the SW0 off and SW1 on to fill out the third row. Slide both of them on to fill out the final row. After you fill out the truth table, you can click button “Check Result” to see if you filled it all out correctly.

    SW1 SW0 LD0
    0 0
    0 1
    1 0
    1 1
  2. Circuit 2

    The second circuit takes SW1, SW2, and SW3 as inputs, and LD1 as output. Probe Circuit 2 the same way you did Circuit 1 and fill out the truth table below. After you fill out the truth table, you can click button “Check Result” to see if you filled it out correctly.

    SW3 SW2 SW1 LD1
    0 0 0
    0 0 1
    0 1 0
    0 1 1
    1 0 0
    1 0 1
    1 1 0
    1 1 1
  3. Circuit 3

    The third circuit takes SW4, SW5, SW6, and SW7 as inputs, and LD2 as output. Probe Circuit 3 the same way you did Circuit 1 and fill out the truth table below. After you fill out the truth table, you can click button “Check Result” to see if you filled it out correctly.

    SW7 SW6 SW5 SW4 LD2
    0 0 0 0
    0 0 0 1
    0 0 1 0
    0 0 1 1
    0 1 0 0
    0 1 0 1
    0 1 1 0
    0 1 1 1
    1 0 0 0
    1 0 0 1
    1 0 1 0
    1 0 1 1
    1 1 0 0
    1 1 0 1
    1 1 1 0
    1 1 1 1

Basic Logic Operations and Their Representations

AND, OR, and NOT (or inversion) are the three primary logic relationships that can be used to express any logical relationship between any number of variables. These simple logic functions form the basis for all digital electronic devices, from a simple microwave oven controller to a desktop PC. There are a set of symbols that are commonly used to express these logic operations. You may have seen some of the symbols in your math classes or in other programming languages. Here is a list for the symbols for the three primary logic relationships:

Logic Operation in Math Class in Real Digital in C Programming
Language
in Circuit Schematic in Verilog HDL
A And B $A\cdot B$
\(A \land B\)
\(A \& B\)
\(A \cdot B\) \(A \& B\) And Gate \(A \& B\)
A Or B \(A \vee B\)
\(A + B\)
\(A | B\)
\(A + B\) \(A | B\) Or Gate \(A | B\)
Not A \(\lnot A\)
\(\sim A\)
\(!A\)
\(A'\)
\(\overline{A}\)
\(\overline{A}\) \(\sim A\) Not Gate \(\sim A\)

Sum of Product (SOP) and Product of Sum (POS) Circuit

A product term is defined as an AND relationship between any number of variables, and a sum term is defined as an OR relationship between any number of logic variables. Any logic system can be represented in two logically equivalent ways: as the OR'ing of AND'ed terms, known as the sum of products (SOP) form; or as the AND'ing of OR'ed terms, known as the product of sums (POS) form.

A logic equation (and therefore a logic circuit) can easily be constructed from any truth table by applying the rules presented below.

For SOP circuits:

  1. A circuit for a truth table with N input columns can use AND gates with N inputs, and each row in the truth table with a “1” in the output column requires one N-input AND gate.
  2. Inputs to the AND gate are inverted if the input shows a “0” on the row, and not inverted if the input shows a “1” on the row.
  3. All AND terms are connected to an M-input OR gate, where M is the number of “1” output rows.
  4. The output of the OR gate is the function output.
Figure 1. Deriving logic expressions in SOP form from the truth table.

For POS circuits:

  1. A circuit for a truth table with N input columns can use OR gates with N inputs, and each row in the truth table with a “0” in the output column requires one N input OR gate.
  2. Inputs to the OR gate are inverted if the input shows a “1” on the row, and not inverted if the input shows a “0” on the row.
  3. All OR terms are connected to an M-input AND gate, where M is the number of “0” output rows.
  4. The output of the AND gate is the function output.
Figure 2. Deriving logic expressions in POS form from the truth table.

Step 3: Re-implement the Logic Function Using Verilog HDL

  1. Create a Vivado project for your board.
  2. Create the top module file with eight switches as input and three LEDs as output. The Verilog code should look like the following:
  3. 		
    					`timescale 1ns/1ps;
    					// Comment 
    					
    					module top (
    					    input [7:0] sw,
    						output [2:0] led
    					);
    					
    					
    					endmodule
    				
  4. Construct and implement logic equation for Circuit 1 according to the truth table.

    We will construct the logic equation in SOP form for demonstration. In Circuit 1, we have two rows (second row and third row) that shows a “1” in the output. So we need an OR gate with two inputs that generate the output, and two 2-input AND gates that provide the input for the OR gate. In the second row, input SW0 shows a “1” and input SW1 shows a “0”. So SW0 is connected to the input of the first AND gate and SW1 is inverted before connecting to the second input of the AND gate, as shown in the first product term in the equation. In the third row, input SW0 shows a “0” and input SW1 shows a “1”. So SW0 is inverted before connecting to the input of the second AND gate and SW1 is connected directly to the second input of the AND gate, as shown in the second product term in the equation. The output LD0 is the summation of these two product terms. \[LD0 = SW0 \cdot \overline{SW1}+ \overline{SW0} \cdot SW1\] In Verilog HDL, this circuit is implemented as follows:

    						assign led[0] = (sw[0] & ~sw[1]) | (~sw[0] & sw[1]);
    					
  5. Construct and implement the logic equation for Circuit 2 according to the truth table.

    Similar to Circuit 1, you can come up with the logic function for the second circuit in SOP form as: \[LD1 = \overline{SW3} \cdot \overline{SW2} \cdot \overline{SW1} + \overline{SW3} \cdot SW2 \cdot SW1 + SW3 \cdot \overline{SW2} \cdot SW1 \] In Verilog HDL, we have:

    						assign led[1] = (~sw[3] & ~sw[2] & ~sw[1]) | (~sw[3] & sw[2] & sw[1]) | (sw[3] & ~sw[2] & sw[1]);
    					
  6. Construct and implement the logic equation for Circuit 3 according to the truth table.

    Similar to Circuit 1, you can come up with the logic function for the second circuit in SOP form as: \[LD1 = \overline{SW7} \cdot \overline{SW6} \cdot \overline{SW5} \cdot SW4 + \overline{SW7} \cdot \overline{SW6} \cdot SW5 \cdot SW4 + \\ \overline{SW7} \cdot SW6 \cdot \overline{SW5} \cdot \overline{SW4} + SW7 \cdot SW6 \cdot SW5 \cdot SW4\] In Verilog HDL, we have:

    						assign led[2] = (~sw[7] & ~sw[6] & ~sw[5] & sw[4]) | (~sw[7] & ~sw[6] & sw[5] & sw[4]) | 
    						                (~sw[7] & sw[6] & ~sw[5] & ~sw[4]) | (sw[7] & sw[6] & sw[5] & sw[4]);
    					
  7. Add the Xilinx Design Constraints for your design.
  8. Program your board and see if the circuit functions the same.

Test Your Knowledge!

Now that you've completed this project, try these modifications:

  • Try to construct POS expressions for Circuit 1 through 3 in the project, and implement them in Verilog HDL. Test it out on the board and see if it functions the same as the pre-compiled bit file.
  • Actually, there is another circuit in the pre-compiled bit file that takes SW3~SW6 as input and LD3 as output. Probe that circuit and construct the logic equations for it. If you find the equation is too long, study the truth table carefully and see if you can make it shorter.

Challenge Problem

  • If you are confident in your ability to configure an FPGA with logic circuits, go ahead and try out the design challenge problem below for some extra practice!

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