In this project, you will design a 4-to-1 mux and a decoder with an enable signal as a “de-mux” to implement a simple serial data transmitter. Both mux and de-mux will be implemented in two Verilog files for future re-use. Another Verilog file will be used to wrap up the mux and de-mux to form a communication system. This hierarchical design methodology will help manage design complexity, promote design reuse, and allow parallel development.
Qty | Description |
---|---|
1 | Digilent® Nexys™4, or Basys™3 FPGA Board |
1 | Xilinx Vivado Design Suite: WebPACK (2014.4 Recommended) |
The word multiplexer has its origins in telecommunications, defining a system where one signal is used to transmit many different messages, either simultaneously or at different times. “Time-multiplexing” describes a system where different messages use the same physical signal, with different messages being sent at different times. A multiplexer can be used as a simple time multiplexer if the select inputs are used to define the time window and the data inputs are used as the data sources. A decoder with an enable can be used as a de-multiplexer.
In the following system diagram in Fig. 1, a 4-to-1 multiplexer selects one on four inputs to pass through to the output, and a de-multiplexer (decoder with enable signal) takes a single input and routes it to one of four outputs.
module mux (
I0, I1, I2, I3, S0, S1, Y
);
input I0, I1, I2, I3, S0, S1;
output reg Y;
// Your behavioral description of Y
// using if-else or case statements
endmodule
A de-multiplexer can be built using a binary decoder with an enable signal. The functional definition of a binary decoder with an enable signal is shown in Fig. 2 below.
module demux (
En, I0, I1, Y0, Y1, Y2, Y3
);
input En, I0, I1;
output reg Y0, Y1, Y2, Y3;
// Your behavioral description of Y
// using if-else or case statements
endmodule
In this step we are going to create the top level module, in which a mux and a de-mux will be instantiated and connected properly to form a simple time multiplexing communication system. The system diagram is shown in Fig. 3 below.
In the block diagram, the input/output ports of the module wrapper is in green; the input/output ports of module mux and demux is displayed in black italic; and the internal wire of wrapper module is in purple.
module wrapper (
I0, I1, I2, I3, S0, S1, Y0, Y1, Y2, Y3
);
input I3, I2, I1, I0, S1, S0;
output Y0, Y1, Y2, Y3;
// Structural Description of wrapper
endmodule
wire sdata;
mux input_mux (
.I3(I3),
.I2(I2),
.I1(I1),
.I0(I0),
.S1(S1),
.S0(S0),
.Y(sdata)
);
demux output_demux (
.En(sdata),
.I1(S1),
.I0(S0),
.Y0(Y0),
.Y1(Y1),
.Y2(Y2),
.Y3(Y3)
);
module wrapper (
I0, I1, I2, I3, S0, S1, Y0, Y1, Y2, Y3
);
input I3, I2, I1, I0, S1, S0;
output Y0, Y1, Y2, Y3;
// Structural Description of wrapper
wire sdata;
mux input_mux (
.I3(I3),
.I2(I2),
.I1(I1),
.I0(I0),
.S1(S1),
.S0(S0),
.Y(sdata)
);
demux output_demux (
.En(sdata),
.I1(S1),
.I0(S0),
.Y0(Y0),
.Y1(Y1),
.Y2(Y2),
.Y3(Y3)
);
endmodule
Now that you've completed this project, try these modifications:
Create a XDC file to map.