Simulate Glitch and Delay

Step 1: Implement the Circuit in Verilog

In this project, we are going to implement a circuit in Verilog and simulate it, taking delay into consideration. The circuit schematic is shown in Fig. 1 below, and the delay of each gate is marked in red.

1. The circuit takes three inputs (A, B, C) and one output (X), so the declaration of the module goes as follows:

   						module CombCirc(
   						   input A,
   						   input B,
   						   input C,
   						   output X
   						   );
   						
   						// Circuit Description
   						
   						endmodule
   					

2. As we need to tell the tools about the delay of each of the gates, we will need to define the name of each internal wire.

   						wire N1, N2, N3;
   					

3. Now we describe each gate in the circuit one by one.

   						// AND gate with 1ns delay
   						assign #1 N1 = A & B;
   						// Not Gate with 1ns delay
   						assign #1 N2 = ~B;
   						// And Gate with 1ns delay
   						assign #1 N3 = N2 & C;
   						// Or Gate with 1ns delay
   						assign #1 X = N1 | N3;
   					

4. The time scale for each delay is in ns, so we need to have `timescale at the beginning of the file:

   						`timescale 1ns / 1ps
   					

5. So the Verilog file that describes the circuit with delay information of each gate looks as follows:

   						`timescale 1ns / 1ps
   						module CombCirc(
   						    input A,
   						    input B,
   						    input C,
   						    output X
   						    );
   						
   						wire N1, N2, N3;
   						
   						// AND gate with 1ns delay
   						assign #1 N1 = A & B;
   						// Not Gate with 1ns delay
   						assign #1 N2 = ~B;
   						// And Gate with 1ns delay
   						assign #1 N3 = N2 & C;
   						// Or Gate with 1ns delay
   						assign #1 X = N1 | N3;
   						
   						endmodule
   					

Step 2: Create the Test Bench and Simulate the Circuit

1. As the purpose of this test bench is to demonstrate the glitch, instead of simulating all of the possible input transitions, we will craft an input sequence that can trigger the glitch in the output of the circuit. By observing the circuit, there is an unbalanced path between input B and output X (i.e., there are two paths to propagate the changes of B to the output with different delays). So the glitch will happen when A and C are constant and B toggles. Here is the description we are going to create in the initial block of Verilog test bench:

   						integer k = 0;
   						
   						initial begin
   							// Initialize Inputs
   							A = 0;
   							B = 0;
   							C = 0;
   						
   							// Wait 100 ns for global reset to finish
   							// Add stimulus here
   						
   							for(k = 0; k < 4; k=k+1)
   							begin
   								{A,C} = k;
   								#5 B = 1;
   								#5 B = 0;
   								#5 ;
   							end
   						end
   					

2. Simulate the test bench in the Vivado Simulator, and you will get the waveform display, as shown in Fig. 2 below. The red circle on the waveform specifies the glitch. So the glitch actually happens when A is 1, C is 1 and B toggles from 1 to 0. The duration of the glitch is 1ns.