In this project, we are going to examine the delay in combinational circuits. We are going to tell the simulator of the delay of each gate in Verilog and simulate the circuits to see how delay can affect the behavior of a combinational circuit.
Qty | Description |
---|---|
1 | Digilent® Nexys™4, or Basys™3 FPGA Board |
1 | Xilinx Vivado Design Suite: WebPACK (2014.4 Recommended) |
In this project, we are going to implement a circuit in Verilog and simulate it, taking delay into consideration. The circuit schematic is shown in Fig. 1 below, and the delay of each gate is marked in red.
module CombCirc(
input A,
input B,
input C,
output X
);
// Circuit Description
endmodule
wire N1, N2, N3;
// AND gate with 1ns delay
assign #1 N1 = A & B;
// Not Gate with 1ns delay
assign #1 N2 = ~B;
// And Gate with 1ns delay
assign #1 N3 = N2 & C;
// Or Gate with 1ns delay
assign #1 X = N1 | N3;
`timescale 1ns / 1ps
`timescale 1ns / 1ps
module CombCirc(
input A,
input B,
input C,
output X
);
wire N1, N2, N3;
// AND gate with 1ns delay
assign #1 N1 = A & B;
// Not Gate with 1ns delay
assign #1 N2 = ~B;
// And Gate with 1ns delay
assign #1 N3 = N2 & C;
// Or Gate with 1ns delay
assign #1 X = N1 | N3;
endmodule
integer k = 0;
initial begin
// Initialize Inputs
A = 0;
B = 0;
C = 0;
// Wait 100 ns for global reset to finish
// Add stimulus here
for(k = 0; k < 4; k=k+1)
begin
{A,C} = k;
#5 B = 1;
#5 B = 0;
#5 ;
end
end
Now that you've completed this project, try these modifications: