Handshaking—What and Why

Handshaking refers to the mechanism to facilitate the transfer of data between two systems that may be operating at different clock frequencies. In simpler terms, it involves a set of messages or signals exchanged between two devices that control when data is transferred. The sender is the device that is the source of the information, and the receiver is the device intended to be the destination of the information. For effective exchange of information, the sender needs to know if the receiver is in a condition in which it is able to receive the information and when the receiver has successfully received the information. The receiver needs to know when the information is ready to be sent and when the sender determines that the receiver has acquired the information.

The exact implementation of the handshaking process comes in many forms, but it may be classified as either explicit or implicit. Explicit handshaking uses dedicated hardware control signals to indicate the impending action from the sender and readiness of the receiving device, as shown in Fig. 1. Each of the two handshaking signals has two possible states. The basic concepts are that the receiving device must indicate when it is ready to receive data and when it is done. The sending device must tell the receiving device when new data is ready and when the data is no longer available.

The timing diagram shown in Fig. 2 illustrates the sequence of events for the sender to transfer data to the receiver using a four-phase handshaking protocol. The shaded area on the data signal indicates intervals when the data level is permitted change from a high to low or low to high. At time “A,” the receiver asserts the RxRdy signal high to indicate to the sender that it is ready to accept data. When the sender has information to send to the receiver, it first asserts the data signals high or low (indicated at time “B”) and then asserts the TxReq signal high at time “C” to indicate the data is now available to be read. The time interval between “B” and “C” is called the data setup time and is specified by the receiving device. At some point in the interval between times “C” and “D,” the receiving device reads the data bus. The receiving device then asserts the RxRdy signal low to indicate to the sender that it has acquired the data. The sending device then asserts the TxReq signal low at time “E” to indicate to the receiver that the data is no longer available on the data bus. The data must not actually change until time “F” to meet the data hold time specified by the receiving device. The minimum time between successive time points marked “A” is called the cycle time. Regardless of how quickly the sender is able to send data, the data maximum exchange rate must conform to the specifications of the receiving device.

For bidirectional data exchanges, the handshaking signal must be mirrored, as illustrated in Fig. 3. Data sent in only one direction (as illustrated in Fig. 1) are called simplex communications. When communications are restricted to one direction at any given time is referred to as half-duplex operation. This is usually the case for devices that share common data signal lines as illustrated in Fig. 3. Full-duplex operation refers to simultaneous bidirectional data exchange and requires separate data signal lines.

A four-phase handshaking scheme can use an explicit strobe signal from the sender to the receiver and implicit handshaking from the receiver to the sender. The sender assumes implicitly that the receiver is ready, provided the timing constraints for the receiving device are met. Figures 4 and 5 show two common four-phase handshaking interfaces. Since Device “A” controls both the timing and the direction of the data flow, the configuration is commonly referred to as master-slave operation. Figures 6 and 7 show the timing for the four-phase handshaking with the receiver with the implication that the device is always ready to receive new data. Additionally, the sending device assumes that the receiving device has acknowledged the data transfer after a specified period of time. In both cases, the interval between B and C is called the data set up time and the interval between D and F is called the data hold time. In Fig. 6, the interval between A and B is called the control setup time and the time between D and E is called the control hold time.

There is also a two-phase handshaking scheme that is beyond the scope of this discussion. The interested reader should refer to the web link at Velocity Reviews to become informed on the differences between four-phase and two-phase handshaking.

LCD Hardware Interface

The general hardware configuration for this project can be found in Fig. 1 of the Parts Configuration link provided in the tab to the right. The shaded components are for reference only, as the LCD will be used in many of the future projects to serve as a local display. Figure 8 shows the PIC™32 port and pin assignments for the interface to the Digilent^® PmodCLP character LCD that uses an LCD controller with operating characteristics common to many character LCD devices. The PmodCLP reference manual references the data sheet for the Samsung^® KS0066. Although LCD units produced by various manufacturers have different number of characters per line and different numbers of display lines, they have an interface that has become a de facto standard. This interface will be discussed in detail in following paragraphs. The display configuration of the PmodCLP unit has two display lines with each line capable of displaying 16 characters.

There are three signals that the microprocessor uses to control the data transfer with the LCD module. The Enable signal is a read or write strobe, depending on whether the Read/!Write signal is high or low. (The “!” character indicates that the signal is active when the signal is asserted low.) The action of the read and write operations is from the perspective of the microprocessor that serves as the master controller. The LCD controller IC has multiple memory banks or data storage areas: the configuration registers, the data display RAM (DDRAM) and the character generation RAM (CGRAM). The register select (RS) signal determines whether data is exchanged with the LCD DDRAM/CGRAM or the configuration registers. In regards to the handshaking discussion above, this interface represents a half-duplex communications scheme. Obviously, the LCD handshaking conforms to what was described for Figs. 4 and 6. There are two versions of the PmodCLP. As noted on the data sheet, the Rev A module requires 5V power, while other revisions use 3.3V power. (Refer to the PmodCLP support documents for additional details. The hardware configuration for this project is displayed in Fig. 1 of the Parts Configuration tab located above. It shows that test point headers are placed in series with the LCD control lines. These test points will allow us to instrument the operations of the LCD handshaking pins to measure the timing parameters.

The LCD read cycle timing provided in Fig. 9 shows that both the RS and R/W signals must be asserted for a period equal to or longer than the time specified by the R/W setup time parameter, t_su, prior to the E signal being asserted high. Also, prior to asserting the E signal high, the processor I/O pins used for the data lines must be set as inputs to avoid both the LCD and the PIC32 I/O pin contending to control the level of the data lines. The processor must assert the E signal high for a minimum time, as specified the period, t_w. After the read data output delay interval (t_D) and prior to the processor asserting the E signal low, the processor will be able to read the data outputs from the LCD. The LCD maintains the data output until the E signal has been asserted low plus the specified read data hold time (t_DH).

Figure 10 shows the timing diagram for the LCD write cycle. The RS and the R/W signals must be asserted for a period equal to or longer than the time specified by the RS and R/W setup time, parameter, t_su, prior to the E signal being asserted high. The diagram shows that the processor is permitted to set the pins used for data as outputs and write the data to the I/O port any time prior to the E signal making a high to low transition provided that this happens at a time equal to or greater than the write data setup time, t_su1. As in the read cycle timing, the processor must assert the E signal high for a minimum time, as specified the period, t_w. The processor is expected to maintain the data on the output pins at constant logic levels for a period equal to or longer than specified by the write data hold time, t_h1.

The minimum time that the read or write operation can be repeated is set by the enable cycle time, t_c. Table 1 provides the values for the timing parameters for both read and write cycles.

Table 1. LCD signal timing.

LCD Software Interface

The PmodCLP LCD reference manual provides essential information for programming and control of the character LCD. Like the hardware setup for the PIC32 microprocessor, the character LCD has an initialization or configuration phase before the operational phase. One approach to software development for this project is to partition the software into six functions or modules, as shown in Fig. 11. Detailed control flow diagrams for the LCD Read and the LCD Write functions are provided by Figs. 12 and 13. that the control flow diagrams only apply for code that use the bit-banging technique for implementing the LCD interface, as discussed in detail below. These LCD read and write functions control the hardware interface and must be specifically written to match the I/O pin connections from the microprocessor to the LCD unit. The remaining four LCD functional blocks depicted in Fig. 11 are not dependent on hardware connections.

As described above, the LCD controller has two sets of memory registers: one for configuring the LCD operations and one for holding the data that generates the LCD display characters. The register select (RS) signal controls which set of memory registers are accessed for both read and write operations. The display memory is further divided into memory for the display of a fixed set of symbols and characters and memory that can be used to generate user defined characters. The display data RAM (DDRAM) is used for displaying the predefined text characters that are defined in the PmodCLP reference manual. By default, all data is written to and read from the DDRAM when the RS signal is high.

The character generator RAM (CGRAM) is used to generate special symbols that can be programmed by the controlling processor. Accessing the CGRAM and generating special LCD symbols and characters is beyond the scope of this project. See LCD Custom Characters for information regarding configuring the LCD for this mode of operation.

The read and write functions depicted in Fig. 11 are the only two functions that directly interface to the LCD hardware. The same LCD byte write function is used whenever sending a byte to the either the data RAM or to the control registers. This is possible because the value at which the RS is to be set is passed to the LCD read and LCD write functions. The advantage of implementing the LCD control in this manner is that doing so limits the hardware specific code to these two functions. This minimizes the amount of code, which results in reduced development time, portability of user code to different applications, and better memory resource utilization.

The LCD configuration sequence is a series of commands written to the LCD after a power-up or CPU reset. Page 3 of the PmodCLP LCD reference manual lists the commands and the timing delays between writing each of the initializing commands. These delays can be implemented using one of the software delay functions that you developed in Project 2. The values that are written to the LCD, shown in Fig. 14, configure the LCD for an 8-bit data interface with a blinking cursor. The cursor address is reset to zero, placing the cursor at the start of the first line. The cursor address automatically increments as new DDRAM data is written to the LCD. The cursor address is the memory address of the DDRAM where the cursor is seen and the location where the next character written to the DDRAM will be displayed.

After initializing, display characters can be written to the LCD. Each LCD character position is assigned a DDRAM address. DDRAM addresses of the first line of the LCD display are from 0 to 0x0F. The addresses of the second display line are from 0x40 to 0x4F. The DDRAM addresses from 0x10 to 0x39 are not used. If a character is written to DDRAM address 0x0F, the LCD will properly display the character in the right-most position of the first line and increment the cursor address to the value 0x10. If additional characters are to be displayed, the cursor address must be first reset to 0x40. The process of repositioning the cursor position is described below.

Figure 15 shows the control flow diagram for displaying a single character on the LCD. Initially, the status of the busy flag is read until the LCD reports that it has been set low. This is accomplished by repeatedly reading the LCD with the RS signal set low and the RW signal set high. The most significant bit (D7) of the data byte read from the LCD represents the busy flag: if this bit is set to a one, the LCD is busy. The seven least significant bits in the byte read from the LCD contain the DDRAM address of the cursor position.

The next step of the CFD shown in Fig. 15 requires testing the binary value of the character passed to this function to determine if it is an ASCII control character. For instance, when either the carriage return (CR) or the new line (NL) ASCII control characters are sent to this function, the code must send the Return Home or the Clear Display command to the LCD by passing either the 0x02 or 0x01 values, respectively, with both the RS and RW signals set low.

If the cursor address value is between 0x10 and 0x3F, the cursor must be repositioned to the start of the second line or to the cursor address 0x40. This is accomplished by writing the new cursor address, 0x40, adding it to the write DDRAM control bit, 0x80, resulting in a value of 0xC0 that is written to the LCD with the RS and RW signals set low. At this point, the program must wait until the busy flag is set to zero before continuing on with the process of writing the next character to the LCD. The busy flag represents a blocking semaphore , or signal, because the processor is held up waiting for the busy flag to clear. Once the LCD busy flag is read as zero, the RS signal must be set high and the RW signal set low, as well as setting the PIC32 PORT E I/O pins zero through seven as outputs so the ASCII value of the character to be displayed can be written to the LCD DDRAM. The control flow diagram shown in Fig. 15 can be modified to implement additional ASCII control characters.

Most LCD modules require multiple milliseconds to complete the CLEAR DISPLAY and RETURN HOME commands. According to the Samsung KS006U data sheet, operations other than READ BUSY FLAG, ADDRESS, CLEAR DISPLAY, and RETURN HOME operations can require up to 43 µs to complete. The READ BUSY FLAG and ADDRESS operations can be completed as quickly as the LCD timing permits, This allows the LCD BUSY FLAG to be polled at the maximum rate provided by the minimum Enable cycle time shown in Table 1. The time to complete any write operation varies from one LCD manufacturer to another, so the particular device data sheet must be examined closely. The Enable cycle time parameter, t_C, shown in Figs. 9 and 10, clearly shows that there is a maximum rate at which the LCD can be accessed. For the PmodCLP, this maximum rate is 2 MHz.

Bit-Banging LCD Interface

Any microprocessor can interface to a character LCD using the technique called “bit-banging.” Bit-banging refers to the process of explicitly setting specific output pins either high or low, as required by the handshaking protocol. This is accomplished using software statements, such as LATxSET and LATxCLR instructions, to control the state of the RS, RW, and E signals. The interface shown in Fig. 8 provides the PIC32 port and pin specifications to allow the LCD control using this method. The code developer needs only to write the software code to set the control direction of the pins used for data and the values of the pins used for control in the sequence described by the control flow diagrams shown in Figs. 12 and 13. For example, Listing 1 is the C code you can use to implement the LCD_read function shown in Fig. 12 using the bit- banging technique. The code in Listing 1 is written under the assumption that the setup and hold requirements are met and no time delays are required to meet setup and hold times. When using a high-speed processor, such as the PIC32 running at 80MHz, additional delays may be needed to meet the minimum timing requirements.

Listing 1. Example bit-banging code for the LCD_read function.

#include <plib.h>		// Defines BIT constants
#define LCD_DATA (BIT_0|BIT_1|BIT_2|BIT_3|BIT_4|BIT_5|BIT_6| BIT_7) // Port E
#define LCD_EN	BIT_5		// Port D
#define LCD_RS	BIT_15		// Port B
#define LCD_RW	BIT_4		// Port D

int LCD_read(int RS)
{
   	int status;
   	PORTSetPinsDigitalIn(IOPORT_E, LCD_DATA); //Set as input to read
   	mPORTDSetBits(LCD_RW); 		  //LCD_RW set high to read LCD
   	if(RS)
mPORTBsetBits(LCD_RS); 	 		   //LCD_RS set high
	else
mPORTBClearBits(LCD_RS); 		   //LCD_RS low
   	mPORTDSetBits(LCD_EN); 		 //Enable set high
/* If the enable time must be extended – a delay must be added here */
	status = mPORTERead(); 		 //Read BF and ADDR from LCD
   	mPORTDClearBits(LCD_EN); 	 //Enable set low
   	return (status);
}  
                

Parallel Master Port LCD Interface

The PIC32 family of processors is enabled with an addressable parallel port called the parallel master port, or PMP. The chipKIT Pro MX7 processor board was designed to take advantage of this resource when interfacing with the PmodCLP LCD. Using the PMP interface to the LCD is an alternative method to the bit-banging approach described above. It is beyond the scope of this project to explain all of the various ways the PMP can be configured. In general, the PMP consists of an eight- or sixteen-bit bidirectional parallel I/O data bus, a dedicated or multiplexed address bus, and control signals to allow read, write, and address latch enable operations.

The purpose of the PMP is to facilitate a single parallel data bus interface with multiple devices. The general architecture of a parallel data bus is shown in Fig. 16. One can easily see the similarities between Figs. 16, 4, and 8. Figure 17 illustrates the connection between the PIC32 PMP signals and the LCD. Note that Fig. 17 conforms to the same pin assignments as that were shown in Fig. 8.

The address bus is configured as a one-bit signal representing address signal A0 connected to the LCD RS input. The PIC32 strobe output pin is connected to the LCD E input and the PIC32 read/write output control pin to the LCD R/W input. The PIC32 pins assigned to the PMP functions are fixed in hardware. Refer to Appendix C of the chipKIT Pro MX7 Reference Manual to determine which pins are used by the PMP.

The first step in using the PIC32 PMP interface is to configure the PMP for the LCD interface. Using the functions provided by the PIC32 peripheral library (Section 17), the PMP is configured with the four parameters in the statements, shown below in Listing 2.

Listing 2. PMP initialization code for LCD interface.

int cfg1 = PMP_ON|PMP_READ_WRITE_EN|PMP_READ_POL_HI|PMP_WRITE_POL_HI;
int cfg2 = PMP_DATA_BUS_8 | PMP_MODE_MASTER1 |
           PMP_WAIT_BEG_1 | PMP_WAIT_MID_2 | PMP_WAIT_END_1;
int cfg3 = PMP_PEN_0;        // only PMA0 enabled
int cfg4 = PMP_INT_OFF;      // no interrupts used
mPMPOpen(cfg1, cfg2, cfg3, cfg4); 

                

The first bit parameter in the variable cfg1 enables the PMP peripheral. The second bit parameter enables both of the PMP read and write operations. The PMP_READ_POL_HI bit with the PMP_WRITE_POL_HI bit results in setting the last two significant bits of the PMCON register, and it indicates that the PMP read/write control is to be high when reading and low when writing. The interpretation of these two bits is conditional on the PMP_MODE_MASTER1 control bits of the PMMODE register and implements the handshaking operation, as illustrated in Fig. 4. The variable cfg2 is written to the PMMODE register. The PMP_DATA_BUS_8 bit control specifies that the data bus is 8 bits. The three PMP_WAIT controls are discussed in detail below.

The cfg3 variable is set for PMP_PEN_0, indicating that only PMP address bit 0 is enabled and is written to the parallel port address register, PMADDR.

The last parameter disables PMP interrupts. If the PMP interrupt is enabled, with the PMP configured for the master mode, an interrupt will be generated on every completed read and write operation. With the PMP interrupt disabled, the PMFLAG will need to be polled to determine when the PMP read and write cycles are completed.

The WAIT controls in the PMP mode register control the timing of the assertion of the RD/WR select signal in relation to the LCD Enable strobe. Each vertical dash line in Fig. 18 represents intervals of the peripheral bus clock period, marked T_PB where the period of T_PB is the inverse of the peripheral bus clock frequency. The number of T_PB periods for the “B” period is specified by PMP_WAIT_BEG_b (1 ≤ b ≤ 4), specified in the PMMODE configuration setting in Listing 2. Likewise, the “M” indicates the number of T_PB periods that the LCD E signal will be active, as specified by PMP_WAIT_MID_m (0 ≤ m ≤ 15). The minimum strobe period is one T_PB. Thus, the total strobe period is PMP_WAIT_MID_x plus one. The E interval in Fig. 18 indicates the number of T_PB periods that the RD/WR signal will retains its value, PMP_WAIT_END_e (1 ≤ e ≤ 4). For the case shown in Fig. 18, the three parameters would be: PMP_WAIT_BEG_4, PMP_WAIT_MID_6, and PMP_WAIT_END_2.

The minimum settings for the three PMP WAIT intervals can be determined by dividing the value for t_SU on the LCD data sheet by T_PB. For example, assume that the peripheral bus clock is configured for 10 MHz. The t_SU specified in the PmodCLP reference manual is 40 ns, resulting in interval B equal to 0.4. Of course, this should be rounded up, so a proper setting is PMP_WAIT_BEG_1. The value for the interval M is computed using the value specified for t_W. In this case, M+1 is equal to 2.5, and after rounding up and subtracting one, M equals 2. Thus, PMP_WAIT_MID_2 can be used. The value for interval E is 0.1, resulting in PMP_WAIT_END_1. Since [(B+[M+1]+E) * T_PB] represents the minimum time to complete an LCD read or write operation. This minimum time must be greater than the LCD enable cycle time, t_C, which is specified as 500 ns. For the configuration described above, [(B+[M+1]+E) * T_PB] = [(5) * 100 ns] = 500 ns, thereby satisfying the LCD timing specifications. If the cycle time is too short, wait periods can be added to any segment within the allowable ranges.

Since the PMP is clocked from the peripheral bus clock, it is likely that the PMP cycle is slower than the core CPU, which means that the PMP also has a busy flag that must be polled before writing or reading the next byte. With the PMP interrupt disabled, the only way to determine if the PMP is ready for the next read or write cycle is to poll the PMP flag. The PMPMasterWrite function provided in the PIC32 Peripheral Library polls the PMP flag to ensure it has been cleared prior to writing. The code for writing to the LCD is shown in Listing 3.

Listing 3. LCD write function using the PMP.

void writeLCD( int addr, char c)    
{
    while( busyLCD());	// Wait for LCD to be ready
    PMPSetAddress( addr);  // Set LCD RS control
    PMPMasterWrite( c);    // initiate write sequence
} // End of writeLCD
                

Reading the PMP requires two successive read operations, as shown in Listing 4.

Listing 4. LCD read function using the PMP.

char readLCD( int addr)
{
    PMPSetAddress( addr);       // Set LCD RS control
    mPMPMasterReadByte();       // initiate dummy read sequence
    return mPMPMasterReadByte();// read actual data
} // End of readLCD

                

For additional details concerning the PIC32 PMP, refer to Section 13 of the PIC32 Family Reference Manual.

Project Tasks

The first task in this project is to write the seven functions using the PMP LCD interface depicted in Fig. 11 so that the LCD will display chipKIT Pro MX7 on the first line and your name (up to 16 characters) on the second line. The function, LCD_puts, was not previously discussed but is shown in Listing 5. The flow diagram for the LCD_putc function is provided in Fig. 15.

Listing 5. Function to write a text string to the LCD.

void LCD_puts(char *char_string)
{
	while(*char_string)	// Look for end of string NULL character
	{
LCD_putc(*char_string);	// Write character to LCD
char_string++;	// Increment string pointer
  	}
} //End of LCD_puts

                

The second task is to determine the actual times for the three parameters: t_SU, t_W, and t_H for your implementation of the LCD interface are in the specified ranges provided in the PmodCLP reference manual. Finally, justify the measured parameters with the setting specified in the PMP configuration using mPMPOpen.

Project Testing

The first task is verified by observing the LCD screen and visually checking that the proper text is displayed on the proper lines of the LCD.

The second task requires measuring the timing of the LCD control and handshaking signals to determine that the LCD minimum timing specifications are satisfied. Figure 19 shows the timing of the RS, R/W and, E signals. Initially, RS is low and RW is high when the E signal is pulsed high, indicating that the LCD busy flag and that the cursor address is being read twice in a row. (Readers should be able to explain why this is expected.) The last enable pulse occurs when RS is set high and R/W is set low, indicating a write operation. Figures 19 and 20 show the LCD handshaking timing when the PMP Bus timing is set for:

config2 = PMP_DATA_BUS_8 | PMP_MODE_MASTER1 |
      		PMP_WAIT_BEG_4 | PMP_WAIT_MID_15 | PMP_WAIT_END_4;

Figure 20 zooms in on the write operation to allow better measurement of the actual t_su, t_W, and t_H times. The falling edge of the R/W signal at marker for 1.1 µs and the rising edge of the E signal at marker for 1.2 µs clearly shows that PMP_WAIT_BEG is set to one times T_PB. The E signal is high for 0.3 µs, (marker 1.2 µs to 1.5 µs) showing that the PMP_WAIT_MID was set to 2. (Remember that there is always at least one T_PB period for the strobe signal. The number of M wait period is added to the one T_PB.) Record the measurements in Table 2 to show that the minimum LCD timing specifications are satisfied.

Table 2. LCD Bus Timing Results.