Logic Minimization

Real Digital Project 4

The requirements for new logic circuit designs are often expressed in some loose, informal manner. For an informal behavioral description to result in an efficient, well designed circuit that meets the stated requirements, appropriate engineering design methods must be developed.

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Introduction to Digilent FPGA-based Boards

Project 2, Exercise 1

This exercise is based off of the material from Read Digital Project 2. There is a link available to download the PDF of the exercise.

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Board Verification and Basic Logic Circuits

Project 2, Exercise 2

This exercise is based off of the material from Real Digital Project 2. You will download a .bit file to your board to configure the FPGA with eight different logic circuits. The circuits use buttons and switches for inputs, and LEDs for outputs. You must probe the logic circuits by applying all possible combinations of input signals, and from the results write logic equations that describe the circuit’s behavior.

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Getting Started with FPGA

Vivado Project 1: Introduction to Vivado

This project sets up your FPGA board for use with Xilinx® Vivado™ and shows you the steps in starting project files. This is a starter project with very little hands-on work with your board, but it is a good reference if you ever forget how to start your projects.

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Switch Controlled LEDs

Vivado Project 2: Use Switches to Control LEDs

In this project, you will design and implement a circuit that controls an LED on your FPGA board with a slide switch. This project demonstrates how to use Verilog HDL to design a digital circuit and implement it on an FPGA board.

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Design Simple Logic Circuit

Vivado Project 3: Guess the Logic

In this project, you will download a bit file to your board to configure the FPGA with four different logic circuits. The circuits use buttons and switches for inputs, and LEDs for outputs. You must probe the logic circuits by applying all possible combinations of input signals. From the results of applying all possible combinations, you will be able to write logic equations that describe the circuits' behaviors. You will then rewrite the equations using Verilog HDL and re-implement them on FPGA and compare the circuit behavior with the given bit-file.

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Simple Combinational Circuit Design

Vivado Project 4: Majority of Five

How could you find a majority of the vote if each voter of five has a switch to vote for yes or no? The logic is fairly simple and will be used in this project. Any time there are three or more of the five who vote yes, then there is a majority and the LED needs to turn on.

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Describe Combinational Logic Behaviorally

Vivado Project 5: Multiplexer, Decoder, Encoder, and Shifter

In this project you will design a multiplexer, a decoder, an encoder, and a shifter using Verilog HDL. Instead of building the circuit using logic operators, you will learn to describe a circuit behaviorally according to the functionality you wish the circuit to perform.

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Hierarchical Design in Verilog

Vivado Project 6: A Simple Communication System

In this project, you will design a 4-to-1 mux and a decoder with an enable signal as a “de-mux” to implement a simple serial data transmitter. Both mux and de-mux will be implemented in two Verilog files for future re-use. Another Verilog file will be used to wrap up the mux and de-mux to form a communication system. This hierarchical design methodology will help manage design complexity, promote design reuse, and allow parallel development.

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Simulate Glitch and Delay

Vivado Project 7: Simulate Glitch and Delay in Combinational Circuits

In this project, we are going to examine the delay in combinational circuits. We are going to tell the simulator of the delay of each gate in Verilog and simulate the circuits to see how delay can affect the behavior of a combinational circuit.

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