Vivado Project 5: Multiplexer, Decoder, Encoder, and Shifter
In this project you will design a multiplexer, a decoder, an encoder, and a shifter using Verilog HDL. Instead of building the circuit using logic operators, you will learn to describe a circuit behaviorally according to the functionality you wish the circuit to perform.
5.97K
Vivado Project 6: A Simple Communication System
In this project, you will design a 4-to-1 mux and a decoder with an enable signal as a “de-mux” to implement a simple serial data transmitter. Both mux and de-mux will be implemented in two Verilog files for future re-use. Another Verilog file will be used to wrap up the mux and de-mux to form a communication system. This hierarchical design methodology will help manage design complexity, promote design reuse, and allow parallel development.
5.27K
Vivado Project 7: Simulate Glitch and Delay in Combinational Circuits
In this project, we are going to examine the delay in combinational circuits. We are going to tell the simulator of the delay of each gate in Verilog and simulate the circuits to see how delay can affect the behavior of a combinational circuit.
5.66K