Propagation delays not only limit the speed at which a circuit can operate, they can also cause unexpected and unwanted transitions in outputs. These unwanted transitions, called “glitches”, result when an input signal changes state, provided the signal takes two or more paths through a circuit and one path has a longer delay than the other.

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Simulate Glitch and Delay

Vivado Project 7: Simulate Glitch and Delay in Combinational Circuits

In this project, we are going to examine the delay in combinational circuits. We are going to tell the simulator of the delay of each gate in Verilog and simulate the circuits to see how delay can affect the behavior of a combinational circuit.

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