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In this project, you will design a multiplexer, a decoder, an encoder, and a shifter using Verilog HDL. Instead of building the circuit using logic operators, you will learn to describe a circuit behaviorally according to the functionality you wish the circuit to perform.

A state diagram with state codes and complete branching conditions contains all information required for the design of optimal next-state and output logic circuits.

A digital circuit represents and manipulates information encoded as electric signals that can assume one of two voltages: logic high (Vdd) or logic low (GND). Here we will dig further into the workings of digital circuits now that you have a better foundation for understanding.

Armed with the basic understanding of FET operation as described in previous sections, it is possible to construct a basic logic circuit that forms the back bone of all digital and computer circuits. These logic circuits will combine one or more input signals to produce an output signal according to the logic function requirements.

Combinational logic circuits use networks of logic gates to produce outputs that change in strict relation to input changes; that is, an output can only change state immediately after an input changes state.

The terms “product” and “sum” have been borrowed from mathematics to describe AND and OR logic operations. Any logic system can be represented in one of these two logic ways.

A digital logic circuit consists of a collection of logic gates; the input signals that drive them, and the output signals they produce. The behavioral requirements of a logic circuit are best expressed through truth tables or logic equations, and any design problem that can be addressed with a logic circuit can be expressed in one of these forms.

Boolean algebra is perhaps the oldest method used to minimize logic equations. It provides a formal algebraic system to manipulate logic equations so that the minimum can be found. A basic understanding of this system is indispensable to the study and analysis of logic circuits.

Truth tables are not very useful for minimizing logic systems, and Boolean algebra has limited utility. Logic graphs offer the easiest and most useful pen-and-paper method of minimizing a logic system.

Situations can arise where a circuit has N input signals, but not all 2N combinations of inputs are possible. Or, if all 2N combinations of inputs are possible, some combinations might be irrelevant.

Entered variable maps simplify the process further by visually minimizing a K-map. The compression of the map makes a multi-variable system much easier to visualize and minimize.

This page will introduce the two major algorithms used to analyze and minimize logic systems. Both are still valid and used algorithms, however, one is more widely used then the other.

The requirements for new logic circuit designs are often expressed in some loose, informal manner. For an informal behavioral description to result in an efficient, well designed circuit that meets the stated requirements, appropriate engineering design methods must be developed.