Hierarchical Design in Verilog

Project 6: A Simple Communication System

In this project, you will design a 4-to-1 Mux and a decoder with an enable signal as a De-Mux to implement a simple serial data transmitter. Both Mux and De-mux will be implemented in two Verilog files for future re-use. Another Verilog file will be used to wrap up the Mux and De-Mux to form a communication sytem. This hierarchical design methodology will help manage design complexity, promote design reuse, and allow parallel development.

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Design Arithmetic Circuits

Project 10: Comparator, Adder, Multiplier, and ALU

In this project, we will design the arithmetic circuits in FPGA. We will build a 4-bit magnitude comparators, a ripple-carry adder, and a multiplier circuit. You can challenge yourself by integrating all those circuits together with some multiplexer to build an arithmetic logic unit (ALU).

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Data Selectors

An in-depth examination of data selectors, or more commonly called multiplexers (or simply muxes).

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