Background and History
Introduces the topic of Verilog® Hardware Description Language (HDL) and explains the history.
6.75K
Module, I/O Ports, Bus, and Assign
An example of how to use Verilog® HDL. Includes information on module, I/O ports, bus, and assign statements.
13.0K
Project 5: Multiplexer, Decoder, Encoder, and Shifter
In this project, you will design a multiplexer, a decoder, an encoder, and a shifter using Verilog HDL. Instead of building the circuit using logic operators, you will learn to describe a circuit behaviorally according to the functionality you wish the circuit to perform.
10.3K
Project 6: A Simple Communication System
In this project, you will design a 4-to-1 Mux and a decoder with an enable signal as a De-Mux to implement a simple serial data transmitter. Both Mux and De-mux will be implemented in two Verilog files for future re-use. Another Verilog file will be used to wrap up the Mux and De-Mux to form a communication sytem. This hierarchical design methodology will help manage design complexity, promote design reuse, and allow parallel development.
16.0K
Project 7: Simulate Glitch and Delay in Combinational Circuits
In this project, we are going to examine the delay in combinational circuits. We are going to tell the simulator of the delay of each gate in Verilog and simulate the circuits to see how delay can affect the behavior of a combinational circuit.
9.50K
Project 9: Blinking LEDs
Flip-flop is an edge-triggered memory circuit. In this project, we will implement a flip-flop behaviorally using Verilog, and use a bunch of flip-flops to implement a clock divider that blinks the LEDs.
25.2K
Project 12: Serial Adder
In this project, we are going to design a serial adder. Serial Adder is a circuit that performs binary addition bit by bit, i.e. instead of presenting both operands at the inputs of an adder at the same time, the operands are fed into the serial adder bit by bit and generates the answer on the fly. To design such a circuit, we are going to use the state diagram as the formalism to describe the behavior of the circuit, and then translate the state diagram into Verilog code.
7.65K