Vivado Project 1: Introduction to Vivado
This project sets up your FPGA board for use with Xilinx® Vivado™ and shows you the steps in starting project files. This is a starter project with very little hands-on work with your board, but it is a good reference if you ever forget how to start your projects.
9.22K
Vivado Project 2: Use Switches to Control LEDs
In this project, you will design and implement a circuit that controls an LED on your FPGA board with a slide switch. This project demonstrates how to use Verilog HDL to design a digital circuit and implement it on an FPGA board.
9.47K
Vivado Project 3: Guess the Logic
In this project, you will download a bit file to your board to configure the FPGA with four different logic circuits. The circuits use buttons and switches for inputs, and LEDs for outputs. You must probe the logic circuits by applying all possible combinations of input signals. From the results of applying all possible combinations, you will be able to write logic equations that describe the circuits' behaviors. You will then rewrite the equations using Verilog HDL and re-implement them on FPGA and compare the circuit behavior with the given bit-file.
6.66K
Vivado Project 4: Majority of Five
How could you find a majority of the vote if each voter of five has a switch to vote for yes or no? The logic is fairly simple and will be used in this project. Any time there are three or more of the five who vote yes, then there is a majority and the LED needs to turn on.
5.34K
Vivado Project 5: Multiplexer, Decoder, Encoder, and Shifter
In this project you will design a multiplexer, a decoder, an encoder, and a shifter using Verilog HDL. Instead of building the circuit using logic operators, you will learn to describe a circuit behaviorally according to the functionality you wish the circuit to perform.
5.97K
Vivado Project 6: A Simple Communication System
In this project, you will design a 4-to-1 mux and a decoder with an enable signal as a “de-mux” to implement a simple serial data transmitter. Both mux and de-mux will be implemented in two Verilog files for future re-use. Another Verilog file will be used to wrap up the mux and de-mux to form a communication system. This hierarchical design methodology will help manage design complexity, promote design reuse, and allow parallel development.
5.26K
Vivado Project 7: Simulate Glitch and Delay in Combinational Circuits
In this project, we are going to examine the delay in combinational circuits. We are going to tell the simulator of the delay of each gate in Verilog and simulate the circuits to see how delay can affect the behavior of a combinational circuit.
5.66K